External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

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ID 847458
Date 7/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 3 FPGA IP 2. Agilex™ 3 FPGA EMIF IP – Introduction 3. Agilex™ 3 FPGA EMIF IP - Configuring and Generating the IP 4. Agilex™ 3 FPGA EMIF IP – Simulating Memory IP 5. Agilex™ 3 FPGA EMIF IP - Validating the IP 6. Agilex 3 FPGA EMIF IP Debugging 7. Document Revision History for External Memory Interfaces (EMIF) IP User Guide A. Agilex™ 3 FPGA EMIF IP – Product Architecture B. Agilex™ 3 FPGA EMIF IP – End-User Signals
1. About the External Memory Interfaces Agilex™ 3 FPGA IP x
1.1. Release Information
2. Agilex™ 3 FPGA EMIF IP – Introduction x
2.1. Agilex™ 3 EMIF IP Protocol and Feature Support 2.2. Protocol and Maximum Interface Width Support 2.3. Agilex 3 EMIF IP Design Flow 2.4. Agilex™ 3 EMIF IP Design Checklist
3. Agilex™ 3 FPGA EMIF IP - Configuring and Generating the IP x
3.1. Creating an EMIF Project 3.2. Generating and Configuring the EMIF IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Synthesizable EMIF Design Example 3.5. EMIF IP LPDDR4 Parameter Descriptions 3.6. Agilex™ 3 FPGA EMIF IP Pin and Resource Planning 3.7. Compiling the Agilex™ 3 EMIF Design Example 3.8. Agilex™ 3 FPGA EMIF IP – Timing Closure 3.9. Agilex™ 3 FPGA EMIF IP – Controller Optimization
3.4. Generating the Synthesizable EMIF Design Example x
3.4.1. Synthesis Design Example
3.5. EMIF IP LPDDR4 Parameter Descriptions x
3.5.1. High-level Configuration Tab 3.5.2. Advanced: Memory Timing Tab 3.5.3. Advanced: Analog Overrides Tab 3.5.4. Example Design Tab 3.5.5. Configuring DQ Pin Swizzling
3.5.5. Configuring DQ Pin Swizzling x
3.5.5.1. Example: DQ Pin Swizzling Within DQS Group for a x32 LPDDR4 Interface 3.5.5.2. Example: Byte Swizzling for x32 LPDDR4 Interface 3.5.5.3. Example: Combining Pin and Byte Swizzling 3.5.5.4. Example: DQ Pin Swizzling Within DQS Group for 2 Channel x16 LPDDR4 Interface 3.5.5.5. Example: Byte Swizzling for 2 Channel x16 LPDDR4 Interface
3.6. Agilex™ 3 FPGA EMIF IP Pin and Resource Planning x
3.6.1. Agilex™ 3 FPGA EMIF IP Interface Pins 3.6.2. Pin Guidelines for Agilex™ 3 FPGA EMIF IP 3.6.3. Agilex™ 3 FPGA EMIF IP Resources
3.6.1. Agilex™ 3 FPGA EMIF IP Interface Pins x
3.6.1.1. Estimating Pin Requirements 3.6.1.2. LPDDR4 Component Options 3.6.1.3. Maximum Number of Interfaces 3.6.1.4. Address and Command Pin Placement for LPDDR4 3.6.1.5. LPDDR4 Data Width Mapping 3.6.1.6. Pin Placement for Agilex™ 3 EMIF IP
3.6.2. Pin Guidelines for Agilex™ 3 FPGA EMIF IP x
3.6.2.1. General Guidelines 3.6.2.2. Specific Pin Connection Requirements 3.6.2.3. Command and Address Signals 3.6.2.4. Clock Signals 3.6.2.5. Pin Swizzling Guidelines
3.6.3. Agilex™ 3 FPGA EMIF IP Resources x
3.6.3.1. OCT 3.6.3.2. PLL
3.8. Agilex™ 3 FPGA EMIF IP – Timing Closure x
3.8.1. Timing Closure 3.8.2. Timing Analysis 3.8.3. PHY or Core 3.8.4. Optimizing Timing
3.9. Agilex™ 3 FPGA EMIF IP – Controller Optimization x
3.9.1. Optimizing Efficiency for Secondary Controller 3.9.2. Interface Standard 3.9.3. Bank Management Efficiency 3.9.4. Data Transfer 3.9.5. Improving Controller Efficiency
3.9.5. Improving Controller Efficiency x
3.9.5.1. Series of Reads or Writes 3.9.5.2. AXI to Memory Mapping 3.9.5.3. Controller Performance Profile
4. Agilex™ 3 FPGA EMIF IP – Simulating Memory IP x
4.1. Simulation Walkthrough 4.2. Generating the EMIF Design Example for Simulation 4.3. Simulation Design Example 4.4. Simulating the Design Example
4.1. Simulation Walkthrough x
4.1.1. Calibration 4.1.2. Simulation Scripts 4.1.3. Functional Simulation with Verilog HDL
5. Agilex™ 3 FPGA EMIF IP - Validating the IP x
5.1. Validating the Design Example with the Test Engine IP 5.2. Checking the EMIF Design Example with the Performance Monitor
6. Agilex 3 FPGA EMIF IP Debugging x
6.1. Interface Configuration Performance Issues 6.2. Functional Issue Evaluation 6.3. Timing Issue Characteristics 6.4. Evaluating FPGA Timing Issues 6.5. Verifying Memory IP Using the Signal Tap Logic Analyzer 6.6. Guidelines for Developing HDL for Traffic Generator 6.7. Debugging with the External Memory Interface Debug Toolkit 6.8. Guidelines for Traffic Generator Status Check 6.9. Hardware Debugging Guidelines 6.10. Categorizing Hardware Issues 6.11. Agilex™ 3 FPGA EMIF IP - Mailbox Support
6.1. Interface Configuration Performance Issues x
6.1.1. Interface Configuration Bottleneck and Efficiency Issues
6.2. Functional Issue Evaluation x
6.2.1. Altera IP Memory Model 6.2.2. Vendor Memory Model 6.2.3. Transcript Window Messages
6.4. Evaluating FPGA Timing Issues x
6.4.1. Evaluating External Memory Interface Timing Issues
6.7. Debugging with the External Memory Interface Debug Toolkit x
6.7.1. Prerequisites for Using the EMIF Debug Toolkit 6.7.2. Configuring a Design to Use the Debug Toolkit 6.7.3. Launching the EMIF Debug Toolkit 6.7.4. Using the EMIF Debug Toolkit
6.7.2. Configuring a Design to Use the Debug Toolkit x
6.7.2.1. Generating a Design Example with the Debug Toolkit
6.7.4. Using the EMIF Debug Toolkit x
6.7.4.1. Running Re-Calibration 6.7.4.2. Running the Test Engine 6.7.4.3. Generating Traffic with the Test Engine IP
6.8. Guidelines for Traffic Generator Status Check x
6.8.1. Status Check Using the Signal Tap Logic Analyzer 6.8.2. Exporting the Status Interface to the Top-Level Design
6.9. Hardware Debugging Guidelines x
6.9.1. Create a Simplified Design that Demonstrates the Same Issue 6.9.2. Measure Power Distribution Network 6.9.3. Measure Signal Integrity and Setup and Hold Margin 6.9.4. Vary Voltage 6.9.5. Operate at a Lower Speed 6.9.6. Determine Whether the Issue Exists in Previous Versions of Software 6.9.7. Determine Whether the Issue Exists in the Current Version of Software 6.9.8. Try A Different PCB 6.9.9. Try Other Configurations 6.9.10. Debugging Checklist
6.10. Categorizing Hardware Issues x
6.10.1. Signal Integrity Issues 6.10.2. Hardware and Calibration Issues
6.10.1. Signal Integrity Issues x
6.10.1.1. Characteristics of Signal Integrity Issues 6.10.1.2. Evaluating Signal Integrity Issues 6.10.1.3. Skew 6.10.1.4. Crosstalk 6.10.1.5. Power System 6.10.1.6. Clock Signals 6.10.1.7. Address and Command Signals 6.10.1.8. Read Data Valid Window and Eye Diagram 6.10.1.9. Write Data Valid Window and Eye Diagram
6.10.2. Hardware and Calibration Issues x
6.10.2.1. Verifying High-Level Configuration 6.10.2.2. Verifying Memory Timing Parameters 6.10.2.3. Verifying the Correct Memory Component Installed 6.10.2.4. Debugging Intermittent Issues
6.11. Agilex™ 3 FPGA EMIF IP - Mailbox Support x
6.11.1. Agilex™ 3 Mailbox Structure and Register Definitions 6.11.2. Accessing Read-Only Registers 6.11.3. Sending a Mailbox Command 6.11.4. IOSSM Mailbox Access Script
6.11.1. Agilex™ 3 Mailbox Structure and Register Definitions x
6.11.1.1. Mailbox Supported Commands 6.11.1.2. Mailbox Command Definitions 6.11.1.3. ECC Syndrome Codes 6.11.1.4. ECC Error Handling
6.11.2. Accessing Read-Only Registers x
6.11.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Through Read-Only Registers 6.11.2.2. Example 2: Reading the Memory Clock Frequency for an Interface
6.11.3. Sending a Mailbox Command x
6.11.3.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox 6.11.3.2. Example 4: Sending ECC_INJECT_ERROR Using the Mailbox and Reading ECC Error Status, ECC Error Buffer Registers
6.11.4. IOSSM Mailbox Access Script x
6.11.4.1. Mailbox Script Overview 6.11.4.2. Running the Mailbox Script
6.11.4.1. Mailbox Script Overview x
6.11.4.1.1. mb_iossm_command.tcl 6.11.4.1.2. mb_user_input.tcl
A. Agilex™ 3 FPGA EMIF IP – Product Architecture x
A.1. Agilex™ 3 EMIF Architecture: Introduction
A.1. Agilex™ 3 EMIF Architecture: Introduction x
A.1.1. Agilex™ 3 EMIF Architecture: I/O Subsystem A.1.2. Agilex™ 3 EMIF Architecture: I/O SSM A.1.3. Agilex™ 3 EMIF Architecture: HSIO Bank A.1.4. Agilex™ 3 EMIF Architecture: I/O Lane A.1.5. Agilex™ 3 EMIF Architecture: Input DQS Clock Tree A.1.6. Agilex™ 3 EMIF Architecture: PHY Clock Tree A.1.7. Agilex™ 3 EMIF Architecture: PLL Reference Clock Networks A.1.8. Agilex™ 3 EMIF Architecture: Clock Phase Alignment A.1.9. User Clock in Different Core Access Modes A.1.10. Agilex™ 3 EMIF Sequencer A.1.11. Agilex™ 3 EMIF Controller A.1.12. Hard Memory Controller A.1.13. Agilex™ 3 EMIF IP for Hard Processor Subsystem (HPS)
A.1.3. Agilex™ 3 EMIF Architecture: HSIO Bank x
A.1.3.1. Narrow Read Transfer Support A.1.3.2. HSIO Sub-Bank Usage
A.1.12. Hard Memory Controller x
A.1.12.1. Hard Memory Controller Features
A.1.13. Agilex™ 3 EMIF IP for Hard Processor Subsystem (HPS) x
A.1.13.1. Restrictions on I/O Bank Usage for Agilex™ 3 EMIF IP with HPS A.1.13.2. Using the Legacy EMIF Debug Toolkit with Agilex™ 3 HPS Interfaces
B. Agilex™ 3 FPGA EMIF IP – End-User Signals x
B.1. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR4 B.2. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR4 B.3. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR4 B.4. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR4 B.5. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR4 B.6. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR4 B.7. s0_axi4_clock_out for External Memory Interfaces (EMIF) IP - LPDDR4 B.8. s1_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR4 B.9. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4 B.10. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4 B.11. io96b0_to_hps for External Memory Interfaces (EMIF) IP - LPDDR4 B.12. io96b1_to_hps for External Memory Interfaces (EMIF) IP - LPDDR4 B.13. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR4 B.14. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4 B.15. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR4 B.16. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR4 B.17. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR4 B.18. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR4 B.19. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR4 B.20. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4 B.21. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR4 B.22. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR4 B.23. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR4
1. About the External Memory Interfaces Agilex™ 3 FPGA IP
2. Agilex™ 3 FPGA EMIF IP – Introduction
3. Agilex™ 3 FPGA EMIF IP - Configuring and Generating the IP
4. Agilex™ 3 FPGA EMIF IP – Simulating Memory IP
5. Agilex™ 3 FPGA EMIF IP - Validating the IP
6. Agilex 3 FPGA EMIF IP Debugging
7. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
A. Agilex™ 3 FPGA EMIF IP – Product Architecture
B. Agilex™ 3 FPGA EMIF IP – End-User Signals

3.5.1. High-level Configuration Tab

The following figure shows the High-level Configuration tab.

This tab contains three groups of parameters: Memory Device, PHY, and Controller. The tables which follow provide descriptions of the parameters on this tab.

Figure 14. High-level Configuration Tab
Table 5.  Group: High-level Configuration / Memory Device
Parameter Name Description
Number of Channels

Specifies the number of channels that the interface should implement. For multi-channel devices, this should always match the number of channels on the device.

Default value is 2

Legal values are: 1, 2

(Identifier: MEM_NUM_CHANNELS)
Data DQ Width

Number of DQ pins per memory channel, used for data.

Default value is 16

Legal values are: 16, 32

(Identifier: MEM_CHANNEL_DATA_DQ_WIDTH)
Die Density

Capacity of each memory die (in Gbits), per channel per die. For dual-die packages, this is the density of each die, not the density of the full package.

Default value is 16

Legal values are: 1, 2, 3, 4, 6, 8, 12, 16

(Identifier: MEM_DIE_DENSITY_GBITS)
CS Width

Specifies the total number of CS pins used by each channel.

Default value is 1

Legal values are: 1, 2

(Identifier: MEM_CHANNEL_CS_WIDTH)
Auto-set Memory Operating Frequency

if true, let IP select max frequency that this configuration can support for the current device speedgrade. If false, user can set custom value for operating frequency.

Default value is true

(Identifier: MEM_OPERATING_FREQ_MHZ_AUTOSET_EN)
Memory Operating Frequency

Specifies the frequency at which the memory interface will run.

Legal values are: 800, 1066.667.

(Identifier: MEM_OPERATING_FREQ_MHZ)
Table 6.  Group: High-level Configuration / PHY
Parameter Name Description
Auto-set PLL Reference Clock Frequency

if true, let IP select max PLL refclk frequency that this configuration can support. If false, user can set custom value for PLL refclk frequency.

Default value is true

(Identifier: PHY_REFCLK_FREQ_MHZ_AUTOSET_EN)
Enable Advanced List of PLL Reference Clock Frequencies

If true, provide extended list of possible refclk values. Otherwise, prune possible list of refclk values to a more reasonable length.

Default value is false

(Identifier: PHY_REFCLK_ADVANCED_SELECT_EN)
Reference Clock Frequency

Specifies the reference clock frequency for the EMIF IOPLL.

(Identifier: PHY_REFCLK_FREQ_MHZ)
AC Placement

Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms I/O BANK and TOP vs BOT part of the I/O BANK). Legal ranges are derived from device floorplan.

Default value is BOT

Legal values are: BOT, TOP, FULL

(Identifier: PHY_AC_PLACEMENT)
Auto-set Mainband Access Mode

if true, let IP select most likely usecase for the PHY_MAINBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN)
Mainband Access Mode

Specifies the path through which the EMIF QHIP mainband interface is exposed to the user. The mainband interface is the AXI4 interface to the memory controller.

Legal values are: ASYNC, SYNC

(Identifier: PHY_MAINBAND_ACCESS_MODE)
Auto-set Sideband Access Mode

if true, let IP select most likely usecase for the PHY_SIDEBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN)
Sideband Access Mode

Specifies the path through which the EMIF QHIP sideband interface is exposed to the user. The sideband interface is the AXI4-Lite interface to the IOSSM.

Legal values are: FABRIC.

(Identifier: PHY_SIDEBAND_ACCESS_MODE)
Pin Swizzle Map

Specifies the swizzle map for the data lanes and pins.

(Identifier: PHY_SWIZZLE_MAP)
Use Debug Toolkit

If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface.

Default value is false

(Identifier: DEBUG_TOOLS_EN)
Instance ID

Instance ID of the EMIF IP. This is useful when using a discovery mechanism over the side-band interface, to identify which EMIF instance's mailbox is at which offset. If expecting to use a discovery mechanism in hardware, this parameter must be set uniquely for all EMIFs that share a sideband. Otherwise, this parameter can be ignored / kept at the default value.

Default value is 0

Legal values are: from 0 to 6

(Identifier: INSTANCE_ID)
Note: When selecting B18A or M12A package, only TOP is available for address and command placement. The B23C package consists of one full IO96 Bank and a top sub-bank. Take note of the intended placement of the EMIF location when generating the EMIF IP.
Table 7.  Group: High-level Configuration / Controller
Parameter Name Description
Use In-Line ECC

Specifies whether in-line ECC is enabled in the controller. When in-line ECC is enabled, the available memory capacity is reduced by one-eighth to store the ECC checkbits. The maximum AXI address is reduced by the same amount.

Default value is false

(Identifier: CTRL_ECC_INLINE_EN)
Use ECC Autocorrection

If ECC is enabled, specifies whether single-bit-errors (SBEs) should be corrected or just reported.

Default value is true

(Identifier: CTRL_ECC_AUTOCORRECT_EN)
Use Data Masking

Specifies whether Data Masking is enabled by the controller. When ECC is enabled, RMWs will occur (to recompute / write ECC), regardless of whether this is enabled.

Default value is false

(Identifier: CTRL_DM_EN)
Use WDBI

Specifies whether write Data-bus-inversion is enabled by the controller.

Default value is false

(Identifier: CTRL_WR_DBI_EN)
Use RDBI

Specifies whether read Data-bus-inversion is enabled by the controller.

Default value is false

(Identifier: CTRL_RD_DBI_EN)
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