External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 847458
Date 7/07/2025
Public

Visible to Intel only — GUID: nkq1738528530637

Ixiasoft

Document Table of Contents

A.1.13. Agilex™ 3 EMIF IP for Hard Processor Subsystem (HPS)

The Agilex™ 3 FPGA EMIF IP can enable the Agilex™ 3 FPGA hard processor subsystem (HPS) to access external DRAM memory devices.

To enable connectivity between the HPS and the Agilex™ 3 EMIF IP, you must create and configure an instance of the EMIF for HPS IP, and connect it to the Agilex™ 3 FPGA hard processor subsystem instance in your system.