External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 847458
Date 7/07/2025
Public
Document Table of Contents

3.5.5. Configuring DQ Pin Swizzling

It is important to strictly follow the pin placement for a given memory topology when assigning pin locations for your EMIF IP.

Do not change the location for the EMIF pin using a .qsf assignment or the pin planner if you need to swap the DQ pins within a DQS group or the DQS group to simplify board design. The EMIF pin location in .qsf assignment must adhere to the LPDDR4 pin placement table in the Pin Guidelines for Agilex™ 3 FPGA EMIF IP section.

There is no flexibility to swap the address command pin location. The T and C pins for the CLK_T and CLK_C, or DQS_T and DQS_N cannot be swapped with each other. EMIF pin (DQ) swizzling and byte lane (DQS group) swizzling is allowed under certain conditions.

The following tables summarize the parameters for pin swizzling and byte swizzling, respectively.

Table 16.  Parameters for Pin Swizzling
Parameter Description
PIN_SWIZZLE_CH<m>_DQS<n>

Used for swizzling DQ pin within DQS group <n> for channel <m>.

For LPDDR4 device widths of x16, you can swizzle each DQ pin within the lower byte and upper byte respectively. You cannot swizzle DQ pin for the lower byte to upper byte and vice versa.

Table 17.  Parameters for Byte Swizzling
Parameter Description
BYTE_SWIZZLE_CH<m>

Used for swizzling DQS group for CH<m> of the interface.

DQ Pin swizzling within each upper byte or lower byte is permitted; no DQ pin swizzling is permitted from lower byte to upper byte, or vice versa.

The following table summarizes the swizzling guide for byte level:

Table 18.  Swizzling Support by Byte level
Data Width Swizzling Guide

LPDDR4 1ch x32

BL0, BL1, BL6 and BL7 are used for DQ lanes. Byte lane swizzling between BL0 and BL1 is allowed, and byte lane swizzling between BL6 and BL7 is allowed.

LPDDR4 2ch x16

Channel 0: BL0 and BL1 are used for DQ lanes. Byte lane swizzling between BL0 and BL1 is allowed. Cross-channel byte lane swizzling is not allowed.
Channel 1: BL6 and BL7 are used for DQ lanes Byte lane swizzling between BL6 and BL7 is allowed. Cross- channel byte lane swizzling is not allowed.