External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 847458
Date 7/07/2025
Public
Document Table of Contents

2.3. Agilex 3 EMIF IP Design Flow

Altera recommends creating an example top-level file with the desired pin outs and all interface IPs instantiated. This enables the Quartus® Prime software to validate the design and resource allocation before PCB and schematic sign off.

You can also follow the flow for initial hardware bring-up testing, using a design example:

  1. Check the Enable performance monitor for channel x parameter to check the performance metrics of the EMIF interfaces.
  2. Assign all pins on the Quartus® Prime design example during the pin-planning stage.
  3. To observe read and write activity in the system, include the Signal Tap Logic Analyzer in the Quartus® Prime design example.

The following figure shows the design flow to provide the fastest out-of-the-box experience with the EMIF IP.

Figure 1. EMIF IP Design Flow