SEU Mitigation User Guide: Agilex™ 3 FPGAs and SoCs

ID 846231
Date 4/07/2025
Public
Document Table of Contents

3.2. SDM ECC Error Signals Behavior

When the Agilex™ 3 device detects an SDM ECC error, the generic_sdm_valid_out signal of the Advanced SEU Detection IP goes high for one clock cycle.

Always monitor the generic_sdm_valid_out signal. When the generic_sdm_valid_out signal goes high, retrieve the SDM ECC error message content from the generic_sdm_data_out signal of the Advanced SEU Detection IP.

For an example of analyzing ECC errors with Signal Tap after injecting the error and retrieving the error data, refer to the related information.