Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

Download PDF
ID 823097
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Functional Description 4. Interfaces 5. HAL Driver for DMA SoC Mode  6. Parameters 7. Registers 8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide
2. Introduction x
2.1. Device Family Support 2.2. Release Information 2.3. Resource Utilization
3. Functional Description x
3.1. DMA PCIe* Mode 3.2. DMA SoC Mode 3.3. Device Port 3.4. Prefetcher Engine 3.5. DMA Arbiter 3.6. DMA Router 3.7. CSRUnit 3.8. Descriptor Handling 3.9. Interrupts 3.10. Reset Initialization Flows 3.11. Transaction Flow
3.1. DMA PCIe* Mode x
3.1.1. Submodules
3.1.1. Submodules x
3.1.1.1. PCIe* TLP Constructor 3.1.1.2. PCIe* TLP ID Generation 3.1.1.3. PCIe TX Credit Controller 3.1.1.4. PCIe* TX Scheduler 3.1.1.5. PCIe TLP Completer 3.1.1.6. PCIe RX Router 3.1.1.7. PCIe* MSI-X Controller 3.1.1.8. PCIe BAR0 3.1.1.9. PCIe Bursting Manager (BAM) 3.1.1.10. Completion Timeout Parser 3.1.1.11. Control Shadow Parser
3.2. DMA SoC Mode x
3.2.1. Interrupt Controller 3.2.2. Host AXI-4 Agent 3.2.3. Host CSR AXI-4 Lite Agent
3.3. Device Port x
3.3.1. ST Source Agent/ST Sink Agent/MM Agent 3.3.2. Descriptor Engine 3.3.3. Agent Controller 3.3.4. Constructor 3.3.5. Responder 3.3.6. Width Adaptation FIFO
3.8. Descriptor Handling x
3.8.1. Link Descriptor 3.8.2. Data Descriptor 3.8.3. Responder Descriptor 3.8.4. Descriptor Chain 3.8.5. Aligned and Unaligned Transfer Support
3.8.2. Data Descriptor x
3.8.2.1. Data Descriptor - H2D Streaming Transfer 3.8.2.2. Data Descriptor - D2H Streaming Transfer 3.8.2.3. Data Descriptor - H2D Memory Transfer
3.8.3. Responder Descriptor x
3.8.3.1. Responder Descriptor - H2D Streaming Transfer 3.8.3.2. Responder Descriptor - D2H Streaming Transfer 3.8.3.3. Responder Descriptor - H2D Memory Transfer
3.8.4. Descriptor Chain x
3.8.4.1. Descriptor Fetch and Status Update Mechanism
3.11. Transaction Flow x
3.11.1. General DMA Operation Flow 3.11.2. Host to Device (H2D) Flow 3.11.3. Device to Host (D2H) Flow 3.11.4. Soft Reset Handshake Flow
4. Interfaces x
4.1. Port List 4.2. DMA PCIe* Mode Interfaces 4.3. DMA SoC Mode Interfaces 4.4. Device Port Interfaces 4.5. Resets 4.6. Clocks
4.2. DMA PCIe* Mode Interfaces x
4.2.1. Application Packet Receive Interface 4.2.2. Application Packet Transmit Interface 4.2.3. Control Shadow Interface 4.2.4. Transmit Flow Control Credit Interface 4.2.5. Completion Timeout Interface 4.2.6. PCIe* Miscellaneous Signals 4.2.7. Control and Status Register Responder Manager Interface 4.2.8. Bursting Manager Interface
4.3. DMA SoC Mode Interfaces x
4.3.1. Host AXI-4 Memory Map Manager Interface 4.3.2. Host AXI-4 Lite CSR Memory Map Subordinate Interface 4.3.3. Interrupt Interface
4.4. Device Port Interfaces x
4.4.1. Device to Host <PORT#> AXI-ST Subordinate Interface 4.4.2. Device to Host <PORT#> Avalon-ST Sink Interface 4.4.3. Host to Device <PORT#> AXI-ST Manager Interface 4.4.4. Host to Device <PORT#> Avalon-ST Source Interface 4.4.5. Host to Device <PORT#> AXI-4 Manager Interface
5. HAL Driver for DMA SoC Mode  x
5.1. Descriptor Indexing  5.2. HAL Public API 
5.1. Descriptor Indexing  x
5.1.1. Data Descriptors  5.1.2. Responders 
5.2. HAL Public API  x
5.2.1. Software Features 5.2.2. intel_ssgdma.c  5.2.3. intel_ssgdma_global.c 5.2.4. intel_ssgdma_device_port.c  5.2.5. intel_ssgdma_descriptor.c 
6. Parameters x
6.1. DMA Settings 6.2. Device Port Settings 6.3. DMA PCIe Mode Settings 6.4. DMA SoC Mode Settings 6.5. Example Design
6.2. Device Port Settings x
6.2.1. H2D MM 6.2.2. H2D ST 6.2.3. D2H ST
7. Registers x
7.1. Global CSR 7.2. MSI-X Memory Space 7.3. Device Port Control Register
1. Terms and Acronyms
2. Introduction
3. Functional Description
4. Interfaces
5. HAL Driver for DMA SoC Mode 
6. Parameters
7. Registers
8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

5.2.1. Software Features

Table 67.  Software FeaturesList of pre-compiler defines for software features can be define in the qsys bsp editor.
Pre-compiler software feature Parameter Description
Polling for completion timeout, interval

add_sw_setting

decimal_number

public_mk_define

completion_poll_cycle

INTEL_SSGDMA_COMPLETION_POLL_TIMEOUT -1

Set timeout when polling for completion.

Set -1 to disable timeout.

Default value is -1.

This should be used with completion_poll_timeout_us.

add_sw_setting

decimal_number

public_mk_define

completion_poll_timeout_µs

INTEL_SSGDMA_COMPLETION_POLL_INTERVAL_US 100

Timeout interval in “µs”.

Only valid if completion_poll_cycle >0.

Default value is 100µs.
Reset prefetcher timeout, interval

add_sw_setting

decimal_number

public_mk_define

polling_timeout_cycle

INTEL_SSGDMA_POLLING_TIMEOUT -1

Set timeout when polling for transfer complete status.

Set -1 to disable timeout.

Default value is -1.

This should be used with INTEL_SSGDMA_POLLING_INTERVAL_US.

add_sw_setting

decimal_number

public_mk_define

reset_prefetcher_timeout_us

INTEL_SSGDMA_RESET_PREFETCHER_INTERVAL_US 100

Timeout interval in “µs”.

Only valid if reset_prefetcher_timeout_cycle > 0.

Default value is 100µs.
Soft paused timeout, interval

add_sw_setting

decimal_number

public_mk_define

soft_paused_timeout_cycle

INTEL_SSGDMA_SOFT_PAUSED_TIMEOUT -1

Set timeout for soft pause.

Set -1 to disable timeout.

Default value is -1.

This should be used with soft_paused_timeout_us.

add_sw_setting

decimal_number

public_mk_define

soft_paused_timeout_us

INTEL_SSGDMA_SOFT_PAUSED_INTERVAL_US 100

Timeout interval in µs.

Only valid if soft_paused_timeout_cycle > 0.

Default value is 100µs.
Soft reset timeout, interval

add_sw_setting

decimal_number

public_mk_define

soft_reset_timeout_cycle

INTEL_SSGDMA_SOFT_RESET_TIMEOUT -1

Set timeout for soft reset.

Set -1 to disable timeout.

Default value is -1.

This should be used with soft_reset_timeout_us.

add_sw_setting

decimal_number

public_mk_define

soft_reset_timeout_us

INTEL_SSGDMA_SOFT_RESET_INTERVAL_US 100

Timeout interval in µs.

Only valid if soft_reset_timeout_cycl > 0.

Default value is 100µs.
Auto configure driver with IP Parameters from hardware

add_sw_setting

decimal_number

public_mk_define

auto_conf_sw

INTEL_SSGDMA_AUTO_CONF_SW false

Enable to auto configure driver with IP parameters from hardware.

Configurations are number of ports and unaligned access. This gives the flexibility to change the hardware without regenerating the software.

Note: Parameters in system.h might not represent the actual configured value in Platform Designer.

If disabled and the hardware configuration does not match with the generated software, the driver blocks all attempts to setup with intel_ssgdma_setup_device_port.

Reset at init

add_sw_setting

decimal_number

public_mk_define

enable_reset_at_init

INTEL_SSGDMA_ENABLE_RESET_AT_INIT false

Enable this to soft reset for during initialization.

This resets the IP with a default parameter after initialization.

Debug message

add_sw_setting

decimal_number

public_mk_define

enable_debug_message

INTEL_SSGDMA_ENABLE_DEBUG_MESSAGE false

Enable this to print debug messages of intel ssgdma to stdout.

CSR byte access

add_sw_setting

boolean_define_only

public_mk_define

csr_byte_access

INTEL_SSGDMA_CSR_BYTE_ACCESS true

If this is disabled, the platform does not support byte or word accesses.
Level Two Title