Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

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ID 823097
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Functional Description 4. Interfaces 5. HAL Driver for DMA SoC Mode  6. Parameters 7. Registers 8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide
2. Introduction x
2.1. Device Family Support 2.2. Release Information 2.3. Resource Utilization
3. Functional Description x
3.1. DMA PCIe* Mode 3.2. DMA SoC Mode 3.3. Device Port 3.4. Prefetcher Engine 3.5. DMA Arbiter 3.6. DMA Router 3.7. CSRUnit 3.8. Descriptor Handling 3.9. Interrupts 3.10. Reset Initialization Flows 3.11. Transaction Flow
3.1. DMA PCIe* Mode x
3.1.1. Submodules
3.1.1. Submodules x
3.1.1.1. PCIe* TLP Constructor 3.1.1.2. PCIe* TLP ID Generation 3.1.1.3. PCIe TX Credit Controller 3.1.1.4. PCIe* TX Scheduler 3.1.1.5. PCIe TLP Completer 3.1.1.6. PCIe RX Router 3.1.1.7. PCIe* MSI-X Controller 3.1.1.8. PCIe BAR0 3.1.1.9. PCIe Bursting Manager (BAM) 3.1.1.10. Completion Timeout Parser 3.1.1.11. Control Shadow Parser
3.2. DMA SoC Mode x
3.2.1. Interrupt Controller 3.2.2. Host AXI-4 Agent 3.2.3. Host CSR AXI-4 Lite Agent
3.3. Device Port x
3.3.1. ST Source Agent/ST Sink Agent/MM Agent 3.3.2. Descriptor Engine 3.3.3. Agent Controller 3.3.4. Constructor 3.3.5. Responder 3.3.6. Width Adaptation FIFO
3.8. Descriptor Handling x
3.8.1. Link Descriptor 3.8.2. Data Descriptor 3.8.3. Responder Descriptor 3.8.4. Descriptor Chain 3.8.5. Aligned and Unaligned Transfer Support
3.8.2. Data Descriptor x
3.8.2.1. Data Descriptor - H2D Streaming Transfer 3.8.2.2. Data Descriptor - D2H Streaming Transfer 3.8.2.3. Data Descriptor - H2D Memory Transfer
3.8.3. Responder Descriptor x
3.8.3.1. Responder Descriptor - H2D Streaming Transfer 3.8.3.2. Responder Descriptor - D2H Streaming Transfer 3.8.3.3. Responder Descriptor - H2D Memory Transfer
3.8.4. Descriptor Chain x
3.8.4.1. Descriptor Fetch and Status Update Mechanism
3.11. Transaction Flow x
3.11.1. General DMA Operation Flow 3.11.2. Host to Device (H2D) Flow 3.11.3. Device to Host (D2H) Flow 3.11.4. Soft Reset Handshake Flow
4. Interfaces x
4.1. Port List 4.2. DMA PCIe* Mode Interfaces 4.3. DMA SoC Mode Interfaces 4.4. Device Port Interfaces 4.5. Resets 4.6. Clocks
4.2. DMA PCIe* Mode Interfaces x
4.2.1. Application Packet Receive Interface 4.2.2. Application Packet Transmit Interface 4.2.3. Control Shadow Interface 4.2.4. Transmit Flow Control Credit Interface 4.2.5. Completion Timeout Interface 4.2.6. PCIe* Miscellaneous Signals 4.2.7. Control and Status Register Responder Manager Interface 4.2.8. Bursting Manager Interface
4.3. DMA SoC Mode Interfaces x
4.3.1. Host AXI-4 Memory Map Manager Interface 4.3.2. Host AXI-4 Lite CSR Memory Map Subordinate Interface 4.3.3. Interrupt Interface
4.4. Device Port Interfaces x
4.4.1. Device to Host <PORT#> AXI-ST Subordinate Interface 4.4.2. Device to Host <PORT#> Avalon-ST Sink Interface 4.4.3. Host to Device <PORT#> AXI-ST Manager Interface 4.4.4. Host to Device <PORT#> Avalon-ST Source Interface 4.4.5. Host to Device <PORT#> AXI-4 Manager Interface
5. HAL Driver for DMA SoC Mode  x
5.1. Descriptor Indexing  5.2. HAL Public API 
5.1. Descriptor Indexing  x
5.1.1. Data Descriptors  5.1.2. Responders 
5.2. HAL Public API  x
5.2.1. Software Features 5.2.2. intel_ssgdma.c  5.2.3. intel_ssgdma_global.c 5.2.4. intel_ssgdma_device_port.c  5.2.5. intel_ssgdma_descriptor.c 
6. Parameters x
6.1. DMA Settings 6.2. Device Port Settings 6.3. DMA PCIe Mode Settings 6.4. DMA SoC Mode Settings 6.5. Example Design
6.2. Device Port Settings x
6.2.1. H2D MM 6.2.2. H2D ST 6.2.3. D2H ST
7. Registers x
7.1. Global CSR 7.2. MSI-X Memory Space 7.3. Device Port Control Register
1. Terms and Acronyms
2. Introduction
3. Functional Description
4. Interfaces
5. HAL Driver for DMA SoC Mode 
6. Parameters
7. Registers
8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

4.4.3. Host to Device <PORT#> AXI-ST Manager Interface

This interface is enabled if the NUM_H2D_ST_PORTS parameter is equal or more than 1 and Interface Type of AXI-ST is selected.

Clock Domain: h2d<PORT#>_st_clk

Reset: h2d<PORT#>_st_resetn

Table 52.  Host to Device AXI-ST Manager Interface
Signal Name Direction Description
h2d<PORT>_st_tvalid OUT Indicates that the source is driving a valid transfer
h2d<PORT>_st_tready IN

Indicates that the sink can accept a transfer in the current cycle

h2d<PORT>_st_tdata

[(H2D_ST<PORT>_DWD-1):0]

 OUT
  • Data interface
  • H2D_ST<PORT>_DWD = 8, 16, 32, 64, 128, 256, 512, 1024

h2d<PORT>_st_tid [(H2D_ST<PORT>_IDWD-1):0]

 OUT
  • Data stream identifier that indicates different streams of data.
  • Default H2D_ST<PORT>_IDWD: 1

h2d<PORT>_st_tkeep

[(H2D_ST<PORT>_DWD/8-1):0]

 OUT
  • A byte qualifier used to indicate whether the content of the associated byte is valid
  • AXI-Streaming bus must be contiguously valid from the beginning until the last data phase
h2d<PORT>_st_tlast OUT

  • Indicates End of Data/Command Transmission

    For video application, this signal is connected internally to the _event mechanism or act as the synchronization event

h2d<PORT>_st_tuser

[(H2D_ST<PORT>_UWD-1):0]

 OUT
  • Optional user-defined sideband information that can be transmitted alongside the data stream.
  • When the Enable TUSER to SOP mapping feature for H2D_ST Port <PORT> option is enabled, you must assert high on the h2d<PORT>_st_tuser bit[0] at beginning of h2d<PORT>_st_tvalid cycle to indicate start of packet.
  • When the Error Width of H2D_ST Port <PORT> parameter is configured to a value between 1 and 8, user-defined errors within h2d<PORT>_st_tuser must be asserted at the h2d<PORT>_st_tlast cycle.
  • You can use this signal to carry the following information:
    h2d<PORT>_st_tuser mapping Enable additional TUSER Ouput for H2D_ST Port <PORT> option is ON
    Enable TUSER to SOP mapping feature for H2D ST Port <PORT> option Error Width of H2D_ST Port <PORT> option

    H2D_ST<PORT>_UWD = Error Width of H2D_ST Port <PORT>

    Bit [Error Width of H2D_ST Port <PORT>-1:0] – user-defined errors.     		OFF 1-8

    H2D_ST<PORT>_UWD = Error Width of H2D_ST Port <PORT>+1

    Bit [0] - start of packet,

    Bit [H2D_ST<PORT>_UWD -1:1] – user-defined errors.     		ON 0-8
Note: This interface does not support AXI Streaming multi-packet mode.
Table 53.  Host to Device <PORT> PTP AXI-ST Subordinate Interface
Signal Name Direction Description
h2d<PORT>_st_ptp_tvalid IN Indicates that the source is driving a valid transfer.
h2d<PORT>_st_ptp_tready OUT

Indicates that the sink can accept a transfer in the current cycle.
h2d<PORT>_st_ptp_tdata [95:0] IN Data interface
h2d<PORT>_st_ptp_tid [(H2D_ST<PORT>_IDWD-1):0] IN Data stream identifier that indicates different streams of data.
Note: Applicable only if you enable the H2D AXI-ST Subordinate port and PTP timestamp writeback.
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