Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

ID 823097
Date 4/07/2025
Public
Document Table of Contents

6.2.2. H2D ST

Table 118.  H2D ST Parameters
Parameter Range Default Description
Number of H2D ST Device Ports 0 to 8 1

Select the number of physical H2D ST device ports.

The combined device port parameter values must be equal or less than 8.

H2D ST Port <n>
Interface Type of H2D ST Port <n> AXI-ST, Avalon-ST AXI-ST Select the interface type of the H2D ST port.
Data Width of H2D ST Port <n> 8, 16, 32, 64, 128, 256, 512, 1024 64 Host to Device Port <n> Streaming Interface Data Width.
Identification Tag Width of H2D ST Port <n> 1-18 1 Host to Device Port <n> AXI-ST Interface Identification Tag Width. Only applicable when AXI-ST Interface Type is selected.
Enable additional TUSER output for H2D ST Port <n> On or Off On Enable additional TUSER output for H2D ST port. Only applicable when AXI-ST Interface Type is selected.
Enable TUSER to SOP mapping feature for H2D ST Port <n> On or Off On Enable TUSER to SOP mapping feature. When this is enabled, the SSGDMA IP asserts high on the h2d<n>_st_tuser bit[0] at beginning of h2d<n>_st_tvalid cycle to indicate start of packet. This parameter is available only when Enable additional TUSER output for H2D ST port <n> parameter is enabled and AXI-ST Interface Type is selected.
Error Width of H2D_ST Port <n> 0-8 0 Host to Device Port <n> interface error width. When you select AXI-ST Interface Type, the error output is mapped to TUSER output of the port.
Enable PTP Timestamp Input for H2D ST Port <n> On or Off Off Enable 96-bit IEEE 1588 PTP (Precision Time Protocol) timestamp input for H2D ST port.