Scalable Scatter-Gather DMA FPGA IP User Guide

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ID 823097
Date 9/22/2025
Public
Document Table of Contents
Document Table of Contents x
1. Product Discontinuance Notification 2. Terms and Acronyms 3. Introduction 4. Functional Description 5. Interfaces 6. HAL Driver for DMA SoC Mode  7. Parameters 8. Registers 9. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide
3. Introduction x
3.1. Device Family Support 3.2. Release Information 3.3. Resource Utilization
4. Functional Description x
4.1. DMA PCIe* Mode 4.2. DMA SoC Mode 4.3. Device Port 4.4. Prefetcher Engine 4.5. DMA Arbiter 4.6. DMA Router 4.7. CSRUnit 4.8. Descriptor Handling 4.9. Interrupts 4.10. Reset Initialization Flows 4.11. Transaction Flow
4.1. DMA PCIe* Mode x
4.1.1. Submodules
4.1.1. Submodules x
4.1.1.1. PCIe* TLP Constructor 4.1.1.2. PCIe* TLP ID Generation 4.1.1.3. PCIe TX Credit Controller 4.1.1.4. PCIe* TX Scheduler 4.1.1.5. PCIe TLP Completer 4.1.1.6. PCIe RX Router 4.1.1.7. PCIe* MSI-X Controller 4.1.1.8. PCIe BAR0 4.1.1.9. PCIe Bursting Manager (BAM) 4.1.1.10. Completion Timeout Parser 4.1.1.11. Control Shadow Parser
4.2. DMA SoC Mode x
4.2.1. Interrupt Controller 4.2.2. Host AXI-4 Agent 4.2.3. Host CSR AXI-4 Lite Agent
4.3. Device Port x
4.3.1. ST Source Agent/ST Sink Agent/MM Agent 4.3.2. Descriptor Engine 4.3.3. Agent Controller 4.3.4. Constructor 4.3.5. Responder 4.3.6. Width Adaptation FIFO
4.8. Descriptor Handling x
4.8.1. Link Descriptor 4.8.2. Data Descriptor 4.8.3. Responder Descriptor 4.8.4. Descriptor Chain 4.8.5. Aligned and Unaligned Transfer Support
4.8.2. Data Descriptor x
4.8.2.1. Data Descriptor - H2D Streaming Transfer 4.8.2.2. Data Descriptor - D2H Streaming Transfer 4.8.2.3. Data Descriptor - H2D Memory Transfer
4.8.3. Responder Descriptor x
4.8.3.1. Responder Descriptor - H2D Streaming Transfer 4.8.3.2. Responder Descriptor - D2H Streaming Transfer 4.8.3.3. Responder Descriptor - H2D Memory Transfer
4.8.4. Descriptor Chain x
4.8.4.1. Descriptor Fetch and Status Update Mechanism
4.11. Transaction Flow x
4.11.1. General DMA Operation Flow 4.11.2. Host to Device (H2D) Flow 4.11.3. Device to Host (D2H) Flow 4.11.4. Soft Reset Handshake Flow
5. Interfaces x
5.1. Port List 5.2. DMA PCIe* Mode Interfaces 5.3. DMA SoC Mode Interfaces 5.4. Device Port Interfaces 5.5. Resets 5.6. Clocks
5.2. DMA PCIe* Mode Interfaces x
5.2.1. Application Packet Receive Interface 5.2.2. Application Packet Transmit Interface 5.2.3. Control Shadow Interface 5.2.4. Transmit Flow Control Credit Interface 5.2.5. Completion Timeout Interface 5.2.6. PCIe* Miscellaneous Signals 5.2.7. Control and Status Register Responder Manager Interface 5.2.8. Bursting Manager Interface
5.3. DMA SoC Mode Interfaces x
5.3.1. Host AXI-4 Memory Map Manager Interface 5.3.2. Host AXI-4 Lite CSR Memory Map Subordinate Interface 5.3.3. Interrupt Interface
5.4. Device Port Interfaces x
5.4.1. Device to Host <PORT#> AXI-ST Subordinate Interface 5.4.2. Device to Host <PORT#> Avalon-ST Sink Interface 5.4.3. Host to Device <PORT#> AXI-ST Manager Interface 5.4.4. Host to Device <PORT#> Avalon-ST Source Interface 5.4.5. Host to Device <PORT#> AXI-4 Manager Interface
6. HAL Driver for DMA SoC Mode  x
6.1. Descriptor Indexing  6.2. HAL Public API 
6.1. Descriptor Indexing  x
6.1.1. Data Descriptors  6.1.2. Responders 
6.2. HAL Public API  x
6.2.1. Software Features 6.2.2. intel_ssgdma.c  6.2.3. intel_ssgdma_global.c 6.2.4. intel_ssgdma_device_port.c  6.2.5. intel_ssgdma_descriptor.c 
7. Parameters x
7.1. DMA Settings 7.2. Device Port Settings 7.3. DMA PCIe Mode Settings 7.4. DMA SoC Mode Settings 7.5. Example Design
7.2. Device Port Settings x
7.2.1. H2D MM 7.2.2. H2D ST 7.2.3. D2H ST
8. Registers x
8.1. Global CSR 8.2. MSI-X Memory Space 8.3. Device Port Control Register
1. Product Discontinuance Notification
2. Terms and Acronyms
3. Introduction
4. Functional Description
5. Interfaces
6. HAL Driver for DMA SoC Mode 
7. Parameters
8. Registers
9. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

5.2.7. Control and Status Register Responder Manager Interface

Control and Status Register Interface to access mapped PCIe* configuration space and registers. Connect this interface to Control and Status Register Responder interface of GTS AXI Streaming Intel® FPGA IP for PCI Express.

Clock Domain: axi_lite_clk

Reset: ss_axi_lite_aresetn

Table 43.  Control and Status Register Responder Interface
Signal Name Direction Description
Write Address Channel
app_ss_lite_csr_awvalid OUT Indicates that the write address channel signals are valid
ss_app_lite_csr_awready IN Indicates that a transfer on the write address channel can be accepted
app_ss_lite_csr_awaddr [SS_CSR_AWD-1:0] OUT The address of the first transfer in a write transaction. The default value of SS_CSR_AWD = 20
app_ss_lite_csr_awprot [2:0] OUT Protection attributes of a write transaction: privilege, security level, and access type
Write Data Channel
app_ss_lite_csr_wvalid OUT Indicates that the write data channel signals are valid
ss_app_lite_csr_wready IN Indicates that a transfer on the write data channel can be accepted
app_ss_lite_csr_wdata [SS_CSR_DWD-1:0] OUT

Write Data

The default value of SS_CSR_DWD=32
app_ss_lite_csr_wstrb [SS_CSR_DWD/8-1:0] OUT Write strobes, indicate which byte lanes hold valid data
Write Response Channel
ss_app_lite_csr_bvalid IN Indicates that the write response channel signals are valid
app_ss_lite_csr_bready OUT Indicates that a transfer on the write response channel can be accepted
ss_app_lite_csr_bresp[1:0] IN Write response, indicates the status of a write transaction
Read Address Channel
app_ss_lite_csr_arvalid OUT Indicates that the read address channel signals are valid
ss_app_lite_csr_arready IN Indicates that a transfer on the read address channel can be accepted
app_ss_lite_csr_araddr [SS_CSR_AWD-1:0] OUT

The address of the first transfer in a read transaction.

The default value of SS_CSR_AWD = 20
app_ss_lite_csr_arprot [2:0] OUT Protection attributes of a read transaction: privilege, security level, and access type
Read Data Channel
ss_app_lite_csr_rvalid IN Indicates that the read data channel signals are valid
app_ss_lite_csr_rready OUT Indicates that a transfer on the read data channel can be accepted
ss_app_lite_csr_rdata [SS_CSR_DWD-1:0] IN

Read data

The default value of SS_CSR_DWD =32
ss_app_lite_csr_rresp[1:0] IN Read response, indicates the status of a read transfer
Level Two Title