AXI Multichannel DMA IP for PCI Express* User Guide

ID 817911
Date 8/11/2025
Public
Document Table of Contents

5.4.11.2. User Configuration Intercept Response Interface (user_cii_resp)

Interface clock: axi_lite_clk
Table 54.  User Configuration Intercept Response Interface (user_cii_resp)
Signal Name Direction Description
user_dma_st_ciiresp_tvalid Input

Application asserts this signal for one clock to indicate that valid data is driven on the dma_user_st_ciiresp_tdata bus.

dma_user_st_ciiresp_tdata[31:0] Input
Override data.
  • CfgWr: this bus contains the data supplied by the application logic to override the write data to the PCIe Hard IP register.
  • CfgRd: this bus contains the data supplied by the application logic to override the data payload of the Completion TLP.
dma_user_st_ciiresp_tdata[32] Input

Override Data Enable.

Application assert this signal to override the CfgWr payload or CfgRd completion using the data supplied by the application logic on the dma_user_st_ciiresp_tdata[31:0] bus.

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