5.3.1. PCIe AXI-ST TX Interface (ss_tx_st)
5.3.2. PCIe AXI-ST RX Interface (ss_rx_st)
5.3.3. Control and Status Register Interface (ss_csr_lite)
5.3.4. Flow Control Credit Interface
5.3.5. Configuration Intercept Interface (CII)
5.3.6. Completion Timeout Interface (ss_cplto)
5.3.7. Function Level Reset Interface
5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.4.1. H2D AXI-ST Source (h2d_st_initatr)
5.4.2. D2H AXI-ST Sink (d2h_st_respndr)
5.4.3. H2D/D2H AXI-MM Master
5.4.4. BAM AXI-MM Master (bam_mm_initatr)
5.4.5. BAS AXI-MM Slave (bas_mm_respndr)
5.4.6. PIO AXI-Lite Master (pio_lite_initiatr)
5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite)
5.4.8. User Event MSI-X (user_msix)
5.4.9. User Event MSI (user_msi)
5.4.10. User Function Level Reset (user_flr)
5.4.11. User Configuration Intercept Interface - EP Only
5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
4.1.1.2.1. PCIe Device
Figure 11. PCIe Multifunction and SR-IOV System Settings Parameters

Parameter | Value | Default Value | Description |
---|---|---|---|
Enable multiple physical functions | On / Off | Off | Enables multiple physical functions |
Total physical functions (PFs) | 1 – 8 | 1 | Sets the number of physical functions This parameter is available when Enable multiple physical functions is On |
Enable SR-IOV support | On / Off | Off | Enable SR-IOV |
Total virtual functions of physical function 0 (PF0VFs) | 0 – 2048 | 0 | Sets the number of VFs to be assigned to Physical Function 0 This parameter is available when Enable SR-IOV support is On |
Number of DMA channels allocated to PF0 | 0 – 512 | 4 | Sets the number of DMA channels allocated to the PF0 |
Number of DMA channels allocated to each VF in PF0 | 0 – 512 | 0 | Sets the number of DMA channels allocated to each VF in PF0 |