AXI Multichannel DMA IP for PCI Express* User Guide

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ID 817911
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. Functional Description 4. Parameters 5. Interfaces 6. Designing with the IP Core 7. Known Issues 8. Revision History for the AXI Multichannel DMA IP for PCI Express* User Guide
1. About This Document x
1.1. Intended Audience 1.2. Conventions 1.3. Terms and Acronyms 1.4. Related Information
2. Introduction x
2.1. Overview 2.2. IP Features 2.3. Device Family Support 2.4. IP and Design Example Support 2.5. Recommended Speed Grade 2.6. Resource Utilization 2.7. Release Information
2.2. IP Features x
2.2.1. Root Port Mode Features 2.2.2. Endpoint Mode Features 2.2.3. Design Example Support
4. Parameters x
4.1. IP Settings 4.2. Design Examples
4.1. IP Settings x
4.1.1. PCIe Settings
4.1.1. PCIe Settings x
4.1.1.1. MCDMA Settings 4.1.1.2. PCI Express / PCI Capabilities 4.1.1.3. Base Address Registers
4.1.1.1. MCDMA Settings x
4.1.1.1.1. Multichannel DMA Mode 4.1.1.1.2. Bursting Master Mode 4.1.1.1.3. Bursting Slave Mode 4.1.1.1.4. BAM+BAS Mode 4.1.1.1.5. BAM+MCDMA Mode 4.1.1.1.6. BAM+BAS+MCDMA Mode
4.1.1.2. PCI Express / PCI Capabilities x
4.1.1.2.1. PCIe Device 4.1.1.2.2. PCIe MSI-X
4.1.1.2.2. PCIe MSI-X x
4.1.1.2.2.1. PCIe PF MSI-X 4.1.1.2.2.2. PCIe VF MSI-X
4.2. Design Examples x
4.2.1. Aligning AXI MCDMA IP Settings with AXI Streaming IP for PCI Express
5. Interfaces x
5.1. System Block Diagram 5.2. Clocks and Resets 5.3. PCIe IP-facing Interfaces 5.4. User-facing Interfaces
5.3. PCIe IP-facing Interfaces x
5.3.1. PCIe AXI-ST TX Interface (ss_tx_st) 5.3.2. PCIe AXI-ST RX Interface (ss_rx_st) 5.3.3. Control and Status Register Interface (ss_csr_lite) 5.3.4. Flow Control Credit Interface 5.3.5. Configuration Intercept Interface (CII) 5.3.6. Completion Timeout Interface (ss_cplto) 5.3.7. Function Level Reset Interface 5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.3.4. Flow Control Credit Interface x
5.3.4.1. Transmit Flow Credit Interface (ss_txcrdt) 5.3.4.2. Receive Flow Control Credit Interface (ss_rxcrdt)
5.3.5. Configuration Intercept Interface (CII) x
5.3.5.1. Configuration Intercept Request Interface (ss_cii_req) 5.3.5.2. Configuration Intercept Response Interface (ss_cii_resp)
5.3.7. Function Level Reset Interface x
5.3.7.1. FLR Received Interface (ss_flrrcvd) 5.3.7.2. FLR Completion Interface (ss_flrcmpl)
5.4. User-facing Interfaces x
5.4.1. H2D AXI-ST Source (h2d_st_initatr) 5.4.2. D2H AXI-ST Sink (d2h_st_respndr) 5.4.3. H2D/D2H AXI-MM Master 5.4.4. BAM AXI-MM Master (bam_mm_initatr) 5.4.5. BAS AXI-MM Slave (bas_mm_respndr) 5.4.6. PIO AXI-Lite Master (pio_lite_initiatr) 5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite) 5.4.8. User Event MSI-X (user_msix) 5.4.9. User Event MSI (user_msi) 5.4.10. User Function Level Reset (user_flr) 5.4.11. User Configuration Intercept Interface - EP Only 5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
5.4.3. H2D/D2H AXI-MM Master x
5.4.3.1. AXI-MM Write (H2D) 5.4.3.2. AXI-MM Read Channel (D2H)
5.4.11. User Configuration Intercept Interface - EP Only x
5.4.11.1. User Configuration Intercept Request Interface (user_cii_req) 5.4.11.2. User Configuration Intercept Response Interface (user_cii_resp)
6. Designing with the IP Core x
6.1. Generating the IP Core 6.2. IP Core Generation Output 6.3. Simulating the IP Core 6.4. Quick Start Guide
6.4. Quick Start Guide x
6.4.1. Design Example Overview 6.4.2. Functional Description 6.4.3. Generating the Design Example 6.4.4. Simulating the Design Example 6.4.5. Testing the Design Example
1. About This Document
2. Introduction
3. Functional Description
4. Parameters
5. Interfaces
6. Designing with the IP Core
7. Known Issues
8. Revision History for the AXI Multichannel DMA IP for PCI Express* User Guide

5.3.1. PCIe AXI-ST TX Interface (ss_tx_st)

The outbound packet towards the link is transmitted through this PCIe AXI-ST TX interface with separate header and data interfaces. These interfaces support up to 4 segments of 256-bits with a maximum of 2 Transaction Layer Packets (TLPs) per cycle.

For information on this interface, refer to Application Logic Guidelines for the AXI Streaming TX Interface in HIP Native Mode (R-Tile) section in the AXI Streaming FPGA IP for PCI Express User Guide.

Interface clock: axi_st_clk

NUM_OF_SEG depends on the data width.

NUM_OF_SEG = DWIDTH / SEG_WIDTH

DWIDTH = NUM_OF_SEG * 256

DWIDTH depends on the PCIe mode selected. It is equal to:
  • 1024 bits for Gen5 1x16.
  • 512 bits for Gen5 1x8, Gen4 1x16, and Gen3 1x16.
  • 256 bits for Gen4 1x8, Gen3 1x8, Gen5 1x4, Gen4 1x4, and Gen3 1x4.
  • 128 bits for Gen4 1x4 and Gen3 1x4.
Table 31.  PCIe AXI-ST TX Interface
Signal Name Direction Description
app_ss_st_tx_tvalid Output

Indicates that the source is driving a valid transfer.
ss_app_st_tx_tready Input

Indicates that the sink can accept a transfer in the current cycle.

Note: The readyLatency parameter defined in Avalon specification is supported. By default, the value is '0'.
app_ss_st_tx_tdata[DWIDTH-1:0] Output

Data interface with configurable width specified by DATA_WIDTH parameter.

Gen5 1x16 DWIDTH: 4 segments x 256 = 1024
app_ss_st_tx_tkeep[DWIDTH/8-1:0] Output

A byte qualifier used to indicate whether the content of the associated byte is valid.

The invalid bytes are allowed only during app_ss_st_tx_tlast cycle.

Note: The sparse tkeep is not allowed.
app_ss_st_tx_tlast Output

Indicates End of Data/Command Transmission
app_ss_st_tx_tuser_last_segment

[NUM_OF_SEG-1:0]

 Output

Indicates the last segment of the packet on tdata bus.

For a packet without data payload, this signal is asserted during the header cycle on tuser_hdr bus.
app_ss_st_tx_tuser_hvalid

[NUM_OF_SEG-1:0]

 Output

Indicates the tuser_hdr is valid in the respective segment.
app_ss_st_tx_tuser_hdr[DWIDTH-1:0] Output

Carries header format for the respective segment.

For the bit positions and mapping, refer to Header Format section in the AXI Streaming FPGA IP for PCI Express User Guide.
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