AXI Multichannel DMA IP for PCI Express* User Guide

ID 817911
Date 8/11/2025
Public
Document Table of Contents

4.1. IP Settings

Table 10.  IP Settings Parameters
Parameter Value Default Value Description
PCIe Mode

Gen5 1x16

Gen4 1x16

Gen3 1x16

Gen5 1x8

Gen4 1x8

Gen3 1x8

Gen5 1x4

Gen4 1x4

Gen3 1x4

Gen5 1x16

Selects the width of the data interface between the transaction layer and the application layer implemented in the PLD fabric, the lane data rate and the lane rate.

Note:
  • The AXI MCDMA IP Parameter Editor does not provide a separate interface for the bifurcated ports. Identical IP configuration settings are used.
  • To select a bifurcated 2x8 or 4x4 mode, go to the Example Designs tab > PCIe Interfaces > PCIe Interface Settings > PCIe Mode.
  • 1x4 and 1x8 PCIe interface modes for the design example are not supported in the current release.
Data Width

1024

512

256

128

1024
Supported data widths per the PCIe mode:
  • Gen5 1x16: 1024 bits
  • Gen4 1x16: 512 bits
  • Gen3 1x16: 512 bits
  • Gen5 1x8: 512 bits
  • Gen4 1x8: 256 bits
  • Gen3 1x8: 256 bits
  • Gen5 1x4: 256 bits
  • Gen4 1x4: 256 bits, 128 bits
  • Gen3 1x4: 256 bits, 128 bits
Port Mode

Native Endpoint

Root Port

Native Endpoint Selects port mode.
Number of Segments

4

2

1

4
Number of segments in data interface. IP Parameter Editor automatically selects a value per the Data Width:
  • 1024 bits: 4
  • 512 bits: 2
  • 256 bits: 2
  • 128 bits: 1
Segment Width 256

128

256

Segment data width.

Fixed at 256 bits for x16 and x8 modes, and 128 bits for x4 mode.

Single Width Mode   Off

Sets the Single Width Mode. IP Parameter Editor automatically sets this to On based on the PCIe Mode and Data Width settings.