5.3.1. PCIe AXI-ST TX Interface (ss_tx_st)
5.3.2. PCIe AXI-ST RX Interface (ss_rx_st)
5.3.3. Control and Status Register Interface (ss_csr_lite)
5.3.4. Flow Control Credit Interface
5.3.5. Configuration Intercept Interface (CII)
5.3.6. Completion Timeout Interface (ss_cplto)
5.3.7. Function Level Reset Interface
5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.4.1. H2D AXI-ST Source (h2d_st_initatr)
5.4.2. D2H AXI-ST Sink (d2h_st_respndr)
5.4.3. H2D/D2H AXI-MM Master
5.4.4. BAM AXI-MM Master (bam_mm_initatr)
5.4.5. BAS AXI-MM Slave (bas_mm_respndr)
5.4.6. PIO AXI-Lite Master (pio_lite_initiatr)
5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite)
5.4.8. User Event MSI-X (user_msix)
5.4.9. User Event MSI (user_msi)
5.4.10. User Function Level Reset (user_flr)
5.4.11. User Configuration Intercept Interface - EP Only
5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
5.3.7.2. FLR Completion Interface (ss_flrcmpl)
Interface clock: axi_lite_clk
Signal Name | Direction | Description |
---|---|---|
app_ss_st_flrcmpl_tvalid | Output | When asserted, indicates a FLR request completed by MCDMA. The signal is valid for one clock cycle. |
app_ss_st_flrcmpl_tdata [21:0] | Output | [2:0] - The PF number of FLR Completion [13:3] - Indicates child VF number of parent PF indicated by PF number. [14] - Indicates completion is from Virtual Function implemented in the slot's Physical Function. [19:15] - The slot number of FLR completion [21:20] – The PF number of FLR Request (PF[4:3]) |