AXI Multichannel DMA IP for PCI Express* User Guide

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ID 817911
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. Functional Description 4. Parameters 5. Interfaces 6. Designing with the IP Core 7. Known Issues 8. Revision History for the AXI Multichannel DMA IP for PCI Express* User Guide
1. About This Document x
1.1. Intended Audience 1.2. Conventions 1.3. Terms and Acronyms 1.4. Related Information
2. Introduction x
2.1. Overview 2.2. IP Features 2.3. Device Family Support 2.4. IP and Design Example Support 2.5. Recommended Speed Grade 2.6. Resource Utilization 2.7. Release Information
2.2. IP Features x
2.2.1. Root Port Mode Features 2.2.2. Endpoint Mode Features 2.2.3. Design Example Support
4. Parameters x
4.1. IP Settings 4.2. Design Examples
4.1. IP Settings x
4.1.1. PCIe Settings
4.1.1. PCIe Settings x
4.1.1.1. MCDMA Settings 4.1.1.2. PCI Express / PCI Capabilities 4.1.1.3. Base Address Registers
4.1.1.1. MCDMA Settings x
4.1.1.1.1. Multichannel DMA Mode 4.1.1.1.2. Bursting Master Mode 4.1.1.1.3. Bursting Slave Mode 4.1.1.1.4. BAM+BAS Mode 4.1.1.1.5. BAM+MCDMA Mode 4.1.1.1.6. BAM+BAS+MCDMA Mode
4.1.1.2. PCI Express / PCI Capabilities x
4.1.1.2.1. PCIe Device 4.1.1.2.2. PCIe MSI-X
4.1.1.2.2. PCIe MSI-X x
4.1.1.2.2.1. PCIe PF MSI-X 4.1.1.2.2.2. PCIe VF MSI-X
4.2. Design Examples x
4.2.1. Aligning AXI MCDMA IP Settings with AXI Streaming IP for PCI Express
5. Interfaces x
5.1. System Block Diagram 5.2. Clocks and Resets 5.3. PCIe IP-facing Interfaces 5.4. User-facing Interfaces
5.3. PCIe IP-facing Interfaces x
5.3.1. PCIe AXI-ST TX Interface (ss_tx_st) 5.3.2. PCIe AXI-ST RX Interface (ss_rx_st) 5.3.3. Control and Status Register Interface (ss_csr_lite) 5.3.4. Flow Control Credit Interface 5.3.5. Configuration Intercept Interface (CII) 5.3.6. Completion Timeout Interface (ss_cplto) 5.3.7. Function Level Reset Interface 5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.3.4. Flow Control Credit Interface x
5.3.4.1. Transmit Flow Credit Interface (ss_txcrdt) 5.3.4.2. Receive Flow Control Credit Interface (ss_rxcrdt)
5.3.5. Configuration Intercept Interface (CII) x
5.3.5.1. Configuration Intercept Request Interface (ss_cii_req) 5.3.5.2. Configuration Intercept Response Interface (ss_cii_resp)
5.3.7. Function Level Reset Interface x
5.3.7.1. FLR Received Interface (ss_flrrcvd) 5.3.7.2. FLR Completion Interface (ss_flrcmpl)
5.4. User-facing Interfaces x
5.4.1. H2D AXI-ST Source (h2d_st_initatr) 5.4.2. D2H AXI-ST Sink (d2h_st_respndr) 5.4.3. H2D/D2H AXI-MM Master 5.4.4. BAM AXI-MM Master (bam_mm_initatr) 5.4.5. BAS AXI-MM Slave (bas_mm_respndr) 5.4.6. PIO AXI-Lite Master (pio_lite_initiatr) 5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite) 5.4.8. User Event MSI-X (user_msix) 5.4.9. User Event MSI (user_msi) 5.4.10. User Function Level Reset (user_flr) 5.4.11. User Configuration Intercept Interface - EP Only 5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
5.4.3. H2D/D2H AXI-MM Master x
5.4.3.1. AXI-MM Write (H2D) 5.4.3.2. AXI-MM Read Channel (D2H)
5.4.11. User Configuration Intercept Interface - EP Only x
5.4.11.1. User Configuration Intercept Request Interface (user_cii_req) 5.4.11.2. User Configuration Intercept Response Interface (user_cii_resp)
6. Designing with the IP Core x
6.1. Generating the IP Core 6.2. IP Core Generation Output 6.3. Simulating the IP Core 6.4. Quick Start Guide
6.4. Quick Start Guide x
6.4.1. Design Example Overview 6.4.2. Functional Description 6.4.3. Generating the Design Example 6.4.4. Simulating the Design Example 6.4.5. Testing the Design Example
1. About This Document
2. Introduction
3. Functional Description
4. Parameters
5. Interfaces
6. Designing with the IP Core
7. Known Issues
8. Revision History for the AXI Multichannel DMA IP for PCI Express* User Guide

4.2.1. Aligning AXI MCDMA IP Settings with AXI Streaming IP for PCI Express

As the AXI MCDMA IP (intel_pcie_axi_mcdma) needs to interface with the AXI Streaming IP for PCI Express* (intel_pcie_ss_axi), IP settings and interfaces of both IPs must be aligned to ensure both IPs can operate smoothly.

The table below covers IP settings that must be aligned between the two IPs. For example, when the Hard IP Mode of the AXI Streaming IP is configured as a Gen3 x4 Interface 128-bit, the PCIe Mode of the AXI MCDMA IP must be aligned and configured to Gen3 1x4.

Table 26.  IP Settings of AXI MCDMA IP and AXI Streaming IP
AXI MCDMA IP Settings AXI Streaming IP Settings Description
IP Settings PCIe Interface Settings  
PCIe Mode Gen5/4/3 1x16 PCIe Mode Gen5/4/3 1x16  
Gen5/4/3 1x8 Gen5/4/3 1x8

Gen5/4/3 2x8

 To generate 1x8, create a quartus.ini file in the project directory with the content: ini_guard=on.
Gen5/4/3 1x4 Gen5/4/3 1x4

Gen5/4/3 4x4

 To generate 1x4, create a quartus.ini file in the project directory with the content: ini_guard=on.
Port Mode Native Endpoint Port Mode Native Endpoint  
Root Port Root Port  
 
Multichannel DMA User Mode  
BAR2 Address Width 4 KBytes - 12 bits BAR2 Type 64-bit prefetchable memory  
...  
8 EBytes - 63 bits BAR2 Size 4 KBytes - 12 bits  
  ...  
  8 EBytes - 63 bits  
Enable multiple physical functions On / Off Enable multiple physical functions On / Off  
Total physical functions (PFs) 1 - 8 Total physical functions (PFs) 1 - 8  
Enable SR-IOV support On / Off Enable SR-IOV support On / Off  
Total virtual functions of physical function 0 - 256 Total virtual functions of physical function 0 - 256  
Enable MSI-X On Enable MSI-X On  
BAR0 Type 64-bit prefetchable memory BAR0 Type 64-bit prefetchable memory  
BAR0 Size 4 MBytes - 22 bits BAR0 Size 4 MBytes - 22 bits  
BAR1/3/4/5 Type Disabled BAR1/3/4/5 Type Disabled  
Expansion ROM Size Disabled Expansion ROM Size Disabled  
... ...  
16 MBytes - 24 bits 16 MBytes - 24 bits  
BAM+MCDMA, BAM+BAS+MCDMA User Modes  
Enable multiple physical functions On / Off Enable multiple physical functions On / Off  
Total physical functions (PFs) 1 - 8 Total physical functions (PFs) 1 - 8  
Enable SR-IOV support On / Off Enable SR-IOV support On / Off  
Total virtual functions of physical function 0 - 256 Total virtual functions of physical function 0 - 256  
Enable MSI-X On Enable MSI-X On  
BAR0 Type 64-bit prefetchable memory BAR0 Type 64-bit prefetchable memory  
BAR0 Size 4 MBytes - 22 bits BAR0 Size 4 MBytes - 22 bits  
BAR2 Type Disabled BAR2 Type Disabled  
64-bit prefetchable memory 64-bit prefetchable memory  
64-bit non-prefetchable memory 64-bit non-prefetchable memory  
BAR2 Size 4 KBytes - 12 bits BAR2 Size 4 KBytes - 12 bits  
... ...  
16 EBytes - 64 bits 16 EBytes - 64 bits  
BAR4 Type Disabled BAR4 Type Disabled BAR4 is needed when BAS is enabled, i.e., in BAM+BAS+MCDMA user mode.
64-bit prefetchable memory 64-bit prefetchable memory
64-bit non-prefetchable memory 64-bit non-prefetchable memory
BAR4 Size 4 KBytes - 12 bits BAR4 Size 4 KBytes - 12 bits
... ...
16 EBytes - 64 bits 16 EBytes - 64 bits
BAR3/5 Type Disabled BAR3/5 Type Disabled  
Expansion ROM Size Disabled Expansion ROM Size Disabled  
... ...  
16 MBytes - 24 bits 16 MBytes - 24 bits  
Endpoint Bursting Master, Bursting Slave, BAM+BAS User Modes  
BAR0/2/4 Type Disabled BAR0/2/4 Type Disabled  
64-bit prefetchable memory 64-bit prefetchable memory  
64-bit non-prefetchable memory 64-bit non-prefetchable memory  
BAR0/2/4 Size 4 KBytes - 12 bits BAR0/2/4 Size 4 KBytes - 12 bits  
... ...  
16 EBytes - 64 bits 16 EBytes - 64 bits  
BAR1/3/5 Type Disabled BAR1/3/5 Type Disabled  
Expansion ROM Size Disabled Expansion ROM Size Disabled  
... ...  
16 MBytes - 24 bits 16 MBytes - 24 bits  
Bursting Slave, BAM+BAS User Modes  
Enable MSI Capability (Native Endpoint mode only) On / Off PF0 Enable MSI On / Off  
Enable ATT (Root Port mode only) On / Off Enable Address Translation Services (ATS) On / Off  

Some of the AXI MCDMA IP interfaces are enabled by default. This requires the corresponding optional interface of the AXI Streaming IP to be enabled so that signals from both IPs can be connected.

Table 27.  Optional Interfaces to be Enabled on the AXI Streaming IP
AXI MCDMA IP Interfaces Enabled by Default AXI Streaming IP Settings
Control Shadow Interface (Native Endpoint mode only) Enable PCIe0 Control Shadow Interface On
Completion Timeout Interface Enable PCIe0 Completion Timeout Interface On
Configuration Intercept Interface (Native Endpoint mode only) Enable PCIe0 Configuration Intercept Interface On
Error Interface Enable PCIe0 Error Interface On

As the axi_st_clk and axi_mm_clk of the AXI MCDMA IP are expected to be driven by coreclkout_hip_toapp of the AXI Streaming IP, the PLD Clock Frequency IP parameter must be configured to be aligned with supported frequencies of the AXI MCDMA IP.

Table 28.  PLD Clock Frequency Settings
AXI MCDMA IP Supported Clock Frequencies AXI Streaming IP Settings
Gen5/4: 400/425/450 MHz PLD Clock Frequency Gen5/4: 400/425/450 MHz
Gen3: 200/250 MHz Gen3: 200/250 MHz
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