F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

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ID 816968
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 50G Ethernet Design Example Description 3. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 50G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 50G Ethernet Design Example Description
3. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

1.5. Simulating the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example Testbench

Compile and simulate the design by running a simulation script from the command prompt.
Before you begin, you must complete the Support-Logic generation to generate the tile files required for simulation.
  1. At the command prompt, change the testbench simulating working directory by running the following command: 
    cd <design_example_dir>/ex_50g_f/sim
  2. Run the IP setup simulation. 
    ip-setup-simulation -quartus-project=../../compilation_test_design/alt_e50_f.qpf
  3. At the command prompt, change the working directory to <design_example_dir>/example_testbench.
  4. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
    Table 3.  Instructions to Simulate the Testbench
    Simulator Command
    Siemens* EDA QuestaSim* vsim -do run_vsim.do.
    Synopsys* VCS* sh run_vcs.sh
    Synopsys* VCS* MX sh run_vcsmx.sh.
    Cadence* Xcelium* sh run_xcelium.sh
    Aldec* Riviera-PRO* vsim -do run_riviera.do
A successful simulation ends with the following message: 
Simulation Passed.
or 
Testbench complete.
After successful completion, you can analyze the results.
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