GTS Serial Lite IV IP Design Example User Guide

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ID 813973
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Analog Parameters
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
1. About the GTS Serial Lite IV IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV IP Design Example User Guide

2.3.2. Directory Structure

The Quartus® Prime Pro Edition software generates the design example files in the following folders:
  • <user_defined_design_example_directory>/ed_sim
  • <user_defined_design_example_directory>/ed_synth
  • <user_defined_design_example_directory>/ed_hwtest

The following diagrams show the directories that contain the generated files for the design example.

Figure 5. Directory Structure for Agilex™ 5 and Agilex™ 3 GTS Serial Lite IV Design Example
Table 4.  Design Example Generated Directory and File Descriptions
Directory/File Description
ed_sim/tb_components The directory that contains the testbench files.
ed_sim/common The directory that contains the .tcl scripts for all the simulators.

ed_sim/cadence

ed_sim/mentor

ed_sim/xcelium

ed_sim/synopsys/vcs

ed_sim/synopsys/vcsmx

The directories that contain the simulation scripts. These directories also serve as a working area for the simulators.

For simplex Tx/Rx mode:

ed_sim/seriallite4_tx_0

ed_sim/seriallite4_rx_0

For duplex mode:

ed_sim/seriallite4_dup

 The directory that contains the design example simulation source files.

ed_sim/seriallite4_tx_0.ip

ed_sim/seriallite4_rx_0.ip

ed_sim/seriallite4_dup.ip

ed_sim/seriallite4_system_pll.ip

 IP-XACT representation of the design.
ed_synth/seriallite_iv_streaming_demo.qpf Quartus® Prime Pro Edition project file.
ed_synth/seriallite_iv_streaming_demo.qsf Quartus® Prime Pro Edition settings file.
ed_synth/seriallite_iv_streaming_demo.sdc Synopsys Design Constraints (SDC) file.
ed_synth/src The directory that contains the design example synthesizable components.
ed_synth/src/seriallite_iv_streaming_demo.v Design example top-level HDL.
ed_synth/demo_control The directory for each synthesizable component including Platform Designer-generated IPs, such as Demo Management and Demo Control modules.
ed_hwtest/sliv_ip_toolkit The directory that contains the .tcl script and package files for the Serial Lite IV IP Toolkit.
ed_hwtest/system_console The directory that contains the system console scripts to provide useful commands for reading statistics and enables you to control various features in the design.
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