Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
ID
813762
Date
5/09/2025
Public
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 3 and Agilex™ 5 SoC Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.12. QSPI Controller Ownership Selection Impact on the HPS Software
3.2.2. External Configuration Host with HPS Flash
Figure 8. External Configuration Host with HPS Flash
An external configuration host provides an SDM configuration bitstream containing the following components:
- SDM configuration firmware
- HPS EMIF I/O configuration data
- HPS FSBL code and HPS FSBL hardware handoff binary
In this system layout, the HPS flash, contains the HPS SSBL, Linux* image device tree information, and the OS file system.
Depending on the boot stage that performs the FPGA configuration, you have the following options for storing the FPGA core and I/O configuration file:
- In the HPS flash partition—The SSBL initiates configuration.
- In the OS file system—The OS initiates configuration
SDM Configuration Host | HPS Flash |
---|---|
Avalon® streaming interface |
SD/eMMC |
JTAG |
|
Avalon® streaming interface |
NAND |
JTAG |