GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

ID 813754
Date 8/04/2025
Public
Document Table of Contents

6.14. VIRTIO PCI* Configuration Access Interface

The VIRTIO PCI* Configuration Access Interface is provided to allow applications to implement the VIRTIO PCI* Configuration Access Data register functionality. The VIRTIO specification allows software to use the VIRTIO PCI* Configuration Access capability register as an alternative method to access VIRTIO device region. When this interface is enabled, the PCIe* Subsystem provides a passage for the HIP's VIRTIO PCI* Configuration Access Interface to application logic. When this interface is disabled, the PCIe* Subsystem internally drops writes from the HIP's VIRTIO PCI* Configuration Access Interface and returns zeros for reads (per the requested byte length).