GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs
ID
813754
Date
8/04/2025
Public
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
3.1. Downloading and Installing Quartus® Prime Software
3.2. Configuring and Generating the GTS AXI Streaming IP
3.3. Configuring and Generating GTS System PLL Clocks IP
3.4. Configuring and Generating GTS Reset Sequencer IP
3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs)
3.6. Simulating the GTS AXI Streaming IP Variant
3.7. Compiling the GTS AXI Streaming IP Variant
4.1. Clocking
4.2. Resets
4.3. PCIe* Hard IP
4.4. Hard IP Interface (IF) Adaptor
4.5. Interrupts
4.6. Transaction Ordering
4.7. TX Non-Posted Metering Requirement on Application
4.8. AXI4-Stream Interface
4.9. Tag Allocation
4.10. Power Management
4.11. Config Retry Status Enable
4.12. Hot-Plug
4.13. Configuration Space Extension
4.14. Page Request Service (EP only)
4.15. Precision Time Measurement (PTM)
4.16. Single Root I/O Virtualization (SR-IOV)
4.17. Transaction Layer Packet (TLP) Bypass Mode
4.18. Scalable IOV
5.2.2.4.1. PCIe0/PCIe1 Device
5.2.2.4.2. PCIe0/PCIe1 Link
5.2.2.4.3. PCIe0/PCIe1 Slot
5.2.2.4.4. PCIe0/PCIe1 Legacy Interrupt Pin Register
5.2.2.4.5. PCIe0/PCIe1 PTM
5.2.2.4.6. PCIe0/PCIe1 LTR
5.2.2.4.7. PCIe0/PCIe1 MSI
5.2.2.4.8. PCIe0/PCIe1 MSI-X
5.2.2.4.9. PCIe0/PCIe1 PASID
5.2.2.4.10. PCIe0/PCIe1 DEV SER
5.2.2.4.11. PCIe0/PCIe1 PRS
5.2.2.4.12. PCIe0/PCIe1 Power Management
5.2.2.4.13. PCIe0/PCIe1 VSEC
5.2.2.4.14. PCIe0/PCIe1 ATS
5.2.2.4.15. PCIe0/PCIe1 TPH
5.2.2.4.16. PCIe0/PCIe1 ACS
5.2.2.4.17. PCIe0/PCIe1 Hot-Plug
5.2.2.4.18. PCIe0/PCIe1 VIRTIO
6.1. Overview
6.2. Clocks and Resets
6.3. AXI4-Stream Interfaces
6.4. Configuration Intercept Interface
6.5. Configuration Extension Bus (CEB) Interface
6.6. Control Shadow Interface
6.7. Transmit Flow Control Credit Interface
6.8. Completion Timeout Interface
6.9. Control and Status Register Responder Interface
6.10. Function Level Reset Interface
6.11. TLP Bypass Error Reporting Interface
6.12. Error Interface
6.13. VF Error Flag Interface
6.14. VIRTIO PCI* Configuration Access Interface
6.15. Precision Time Measurement (PTM) Interface
6.16. Serial Data Signals
6.17. Miscellaneous Signals
7.6.1. VF PCI-Compatible Configuration Space Header Type0
7.6.2. VF PCI Express* Capability Structure
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure
7.6.4. VF Alternative Routing ID (ARI) Capability Structure
7.6.5. VF TLP Processing Hints (TPH) Capability Structure
7.6.6. VF Address Translation Services (ATS) Capability Structure
7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.2.1. PCI Express* Capability List Register
7.6.2.2. PCI Express* Device Capabilities Register
7.6.2.3. PCI Express* Device Control and Status Register
7.6.2.4. Link Capabilities Register
7.6.2.5. Link Control and Status Register
7.6.2.6. PCI Express* Device Capabilities 2 Register
7.6.2.7. PCI Express* Device Control and Status 2 Register
7.6.2.8. Link Capabilities 2 Register
7.6.2.9. Link Control and Status 2 Register
5.1. System Settings
Figure 39. Example System Settings Tab in the GTS AXI Streaming IP Parameter Editor
Parameter | Value | Default Setting | Description | |
---|---|---|---|---|
System Settings | ||||
PCIe* 0 Hard IP Mode |
|
Gen3 x4 Interface 128 bit |
Selects the width of the data interface between the transaction layer and the application layer implemented in the PLD fabric, the lane data rate, and the lane rate. |
|
PCIe* 1 Hard IP Mode |
|
Disabled | Selects the width of the data interface between the transaction layer and the application layer implemented in the PLD fabric, the lane data rate, and the lane rate. The Gen4x8 and Gen3x8 options are available when PCIe* 0 Hard IP Mode is set to Disabled.
Note: This option is only available in the D-Series FPGAs.
|
|
PCIe* 0 Enable TLP-bypass mode |
|
False | Enables the TLP Bypass feature for PCIe* 0. |
|
PCIe* 1 Enable TLP-bypass mode |
|
False |
Enables the TLP Bypass feature for PCIe* 1.
Note: This option is only available in the D-Series FPGAs.
|
|
PCIe* 0 Port Mode |
When you set Enable TLP-bypass mode to false, the following values are available:
|
Native Endpoint | Selects the port mode for PCIe* 0. |
|
When you set Enable TLP-bypass mode to true, the following values are available:
|
Upstream Port | |||
PCIe* 1 Port Mode |
When you set Enable TLP-bypass mode to false, the following values are available:
|
Native Endpoint |
Selects the port mode for PCIe* 1.
Note: This option is only available in the D-Series FPGAs.
|
|
When you set Enable TLP-bypass mode to true, the following values are available:
|
Upstream Port | |||
PLD Clock Frequency |
|
300 MHz | Selects the PLD clock frequency.
Note:
|
|
Enable SRIS Mode |
|
False | Enables the Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) feature. |
|
Enable PIPE Mode Simulation |
|
False | When selected, the PIPE mode simulation is enabled.
Note: This parameter is not supported for Quartus® Prime compilation.
The PIPE mode simulation is not supported for QuestaSim* FPGA Edition. When running simulations with this parameter enabled, the following macro is required with the FASTSIM mode enabled: "+define+SM_PIPE_MODE" |
|
Enable CVP (Altera VSEC) |
|
False | Enables CvP for the device. |