GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

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ID 813754
Date 8/04/2025
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. Device Family Support 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks IP 3.4. Configuring and Generating GTS Reset Sequencer IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.10. Power Management x
4.10.1. Endpoint D3 Entry 4.10.2. Endpoint L2 Exit
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
5. IP Parameters x
5.1. System Settings 5.2. PCIe0/PCIe1 5.3. Diagnostics
5.2. PCIe0/PCIe1 x
5.2.1. Interfaces Port 0/Interfaces Port 1 5.2.2. PCIe0/PCIe1 Settings
5.2.1. Interfaces Port 0/Interfaces Port 1 x
5.2.1.1. AXI Interfaces 0/AXI Interface 1 Settings
5.2.2. PCIe0/PCIe1 Settings x
5.2.2.1. PCIe0/PCIe1 Configuration, Debug and Extension Options 5.2.2.2. PCIe0/PCIe1 Base Address Registers 5.2.2.3. PCIe0/PCIe1 Device Identification Registers 5.2.2.4. PCIe0/PCIe1 PCI Express / PCI Capabilities
5.2.2.4. PCIe0/PCIe1 PCI Express / PCI Capabilities x
5.2.2.4.1. PCIe0/PCIe1 Device 5.2.2.4.2. PCIe0/PCIe1 Link 5.2.2.4.3. PCIe0/PCIe1 Slot 5.2.2.4.4. PCIe0/PCIe1 Legacy Interrupt Pin Register 5.2.2.4.5. PCIe0/PCIe1 PTM 5.2.2.4.6. PCIe0/PCIe1 LTR 5.2.2.4.7. PCIe0/PCIe1 MSI 5.2.2.4.8. PCIe0/PCIe1 MSI-X 5.2.2.4.9. PCIe0/PCIe1 PASID 5.2.2.4.10. PCIe0/PCIe1 DEV SER 5.2.2.4.11. PCIe0/PCIe1 PRS 5.2.2.4.12. PCIe0/PCIe1 Power Management 5.2.2.4.13. PCIe0/PCIe1 VSEC 5.2.2.4.14. PCIe0/PCIe1 ATS 5.2.2.4.15. PCIe0/PCIe1 TPH 5.2.2.4.16. PCIe0/PCIe1 ACS 5.2.2.4.17. PCIe0/PCIe1 Hot-Plug 5.2.2.4.18. PCIe0/PCIe1 VIRTIO
5.2.2.4.10. PCIe0/PCIe1 DEV SER x
5.2.2.4.10.1. Implementing Device Serial Number (DSN) with Runtime Update Support
5.2.2.4.18. PCIe0/PCIe1 VIRTIO x
5.2.2.4.18.1. PCIe0/PCIe1 PF<n> VIRTIO STRUCTURES
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Altera-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
B. PIPE Mode Simulation x
B.1. PIPE Mode Interfaces
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

B.1. PIPE Mode Interfaces

The PIPE mode TX and RX interface signals are described in the following tables.
Table 130.  TX PIPE Interfacen= [Lane number]
Signal Direction Description
o_txpipe<n>_asyncpowerchangeack Output Acknowledgement of asynchronous i_rxpipe<n>_phystatus feedback for powerdown state change complete. Signal remains asserted until i_rxpipe<n>_phystatus is de-asserted.
o_txpipe<n>_blockaligncontrol Output

When asserted, enables EIEOS detection in the PHY. EIEOS detection is one of the mechanisms used to control the block aligner in the PHY. This signal is used at the 8.0 GT/s signaling rate.
o_txpipe<n>_cfg_hw_auto_sp_dis Output Autonomous speed disable. Used in downstream ports only.
o_txpipe<n>_dirchange Output
Indicates the PHY to perform Figure Of Merit or Direction Change evaluation.
  • 0: when o_txpipe<n>_rxeqeval = 1, the PHY performs figure of merit
  • 1: when o_txpipe<n>_rxeqeval = 1, the PHY performs direction change
o_txpipe<n>_ebuf_mode Output
Selects elastic buffer mode:
  • 0: Nominal half full
  • 1: Nominal empty
o_txpipe<n>_encodedecodebypass Output When asserted, indicates the PHY to bypass encode and decode operations.
o_txpipe<n>_fs[5:0] Output Provides the FS value advertised by the link partner.
o_txpipe<n>_getlocalpresetcoefficients Output

This field is used to request a preset to coefficient mapping for the preset on o_txpipe<n>_localpresetindex to coefficients on i_rxpipe<n>_localtxpresetcoefficients.
o_txpipe<n>_invalidrequest Output When asserted, indicates that the Link Evaluation feedback requested a link partner TX EQ setting that was out of range.
o_txpipe<n>_lf[5:0] Output Provides the LF value advertised by the link partner.
o_txpipe<n>_localpresetindex[4:0] Output
Indicates the index for the local PHY preset coefficients requested by the MAC and is encoded as follows:
  • ‘b00000- 8 GT/s Preset P0
  • ‘b00001- 8 GT/s Preset P1
  • ‘b00010- 8 GT/s Preset P2
  • ‘b00011- 8 GT/s Preset P3
  • ‘b00100- 8 GT/s Preset P4
  • ‘b00101- 8 GT/s Preset P5
  • ‘b00110- 8 GT/s Preset P6
  • ‘b00111- 8 GT/s Preset P7
  • ‘b01000- 8 GT/s Preset P8
  • ‘b01001- 8 GT/s Preset P9
  • ‘b01010- 8 GT/s Preset P10
  • ‘b01011- 16 GT/s Preset P0
  • ‘b01100- 16 GT/s Preset P1
  • ‘b01101- 16 GT/s Preset P2
  • ‘b01110- 16 GT/s Preset P3
  • ‘b01111- 16 GT/s Preset P4
  • ‘b10000- 16 GT/s Preset P5
  • ‘b10001- 16 GT/s Preset P6
  • ‘b10010 - 16 GT/s Preset P7
  • ‘b10011 - 16 GT/s Preset P8
  • ‘b10100 - 16 GT/s Preset P9
  • ‘b10101 - 16 GT/s Preset P10
o_txpipe<n>_lowpin_nt Output
Select for PIPE Interface:
  • 0: Use Legacy Pin Interface.
  • 1: Use Low Pin Count (Message Bus) Interface.
o_txpipe<n>_m2p_bus[7:0] Output MAC to PHY Communication Bus.
o_txpipe<n>_pclk_rate[2:0] Output
Controls the PIPE PCLK rate:
  • 0: 62.5 MHz
  • 1: 125 MHz
  • 2: 250 MHz
  • 3: 500 MHz
  • 4: 1000 MHz
  • 5: 2000 MHz
  • 6: Reserved
  • 7: Reserved
o_txpipe<n>_pclkchangeack Output

Asserted when a PCLK rate change is complete and stable. After this signal is asserted, the PHY responds by asserting i_rxpipe<n>_phystatus for one cycle and de-asserting i_rxpipe<n>_pclkchangeok at the same time. This signal is de-asserted when i_rxpipe<n>_pclkchangeok is sampled low.
o_txpipe<n>_phy_mode_nt[3:0] Output
The PHY supports mode:
  • 0: PCIe* mode
  • 1: USB mode
o_txpipe<n>_powerdown[3:0] Output
Power control bits that drive the PHY power state. Power states are as follows:
  • 0000: P0 (L0): normal
  • 0001: P0s (L0s): low recovery time, power saving.
  • 0010: P1 (L1): longer recovery time, additional power saving.
  • 0011: P2 (L2): lowest power state.
o_txpipe<n>_rate[2:0] Output
Controls the link signaling rate:

  • 000: Gen1 (2.5 GT/s)

    001: Gen2 (5.0 GT/s)

    010: Gen3 (8.0 GT/s)

    011: Gen4 (16GT/s)

    100-111: Reserved
o_txpipe<n>_rxelecidle_disable_a Output Instructs the PHY to disable the receiver Electrical Idle detection logic.
o_txpipe<n>_rxeqclr Output

When asserted, previously stored PCIe* Gen3.0 RX equalization values are cleared from previous EQ routines.
o_txpipe<n>_rxeqeval Output
Start the evaluation of the receive equalizer digital calibration for the PHY. During this time, the recovered data from the PHY is not guaranteed to be accurate.
  • 0: Disables receive equalizer digital calibration
  • 1: Enables receive equalizer digital calibration
o_txpipe<n>_rxeqinprogress Output When asserted, indicates that the link equalization evaluation is in progress.
o_txpipe<n>_rxeqtraining Output

When asserted, instructs the receiver to bypass normal operation to perform equalization training.
o_txpipe<n>_rxpolarity Output
Directs the PHY to perform a polarity inversion on the received data:
  • 0: No polarity inversion
  • 1: Polarity inversion
o_txpipe<n>_rxpresethint[2:0] Output Provides the RX equalization preset hint for the receiver.
o_txpipe<n>_rxstandby Output
Determines if the PHY RX is active when the PHY is in P0 or P0s.
  • 0: Active
  • 1: Standby
o_txpipe<n>_rxtermination Output Reserved.
o_txpipe<n>_srisenable Output
When asserted, directs the PHY to configure itself to support Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS).
  • 0: SRNS (Separate Refclk with No SSC)
  • 1: SRIS (Separate Refclk with Independent SSC)
o_txpipe<n>_txcmnmode_disable_a Output Instructs the PHY to disable the transmitter common mode logic.
o_txpipe<n>_txcompliance Output Sets the running disparity to negative. Used when transmitting compliance pattern.
o_txpipe<n>_txdata[39:0] Output

Parallel data for transmission.

  • Bits 7:0 correspond to the first symbol of the lane.
  • Bits 15:8 correspond to the second symbol of the lane.
  • Bits 39:16 are unused.
o_txpipe<n>_txdatak[3:0] Output
Control (K character) indicator bits for transmitted data:
  • Bit 0 corresponds to the first symbol of the lane.
  • Bit 1 corresponds to the second symbol of lane the lane.
  • Bit 3:2 are unused.
  • 0: Indicates a data byte
  • 1: Indicates a control byte
o_txpipe<n>_txdatavalid Output Instructs the PHY to ignore the data interface for one or two clock cycles. A value of one indicates that the data is valid and you can use the data.
o_txpipe<n>_txdeemph[17:0] Output

Conveys the transmitter equalization coefficients.

When the rate is 2.5 or 5.0 GT/s:
  • 0: -6 dB de-emphasis
  • 1: -3.5 dB de-emphasis
  • 2: No de-emphasis
  • 3: Reserved
When the rate is 8.0 GT/s, 16 GT/s:
  • [5:0]: C-1 (Pre-cursor)
  • [11:6]: C0 (Cursor)
  • [17:12]: C+1 (Post-cursor).
o_txpipe<n>_txdtctrx_lb Output

Requests the PHY to begin a receiver detection operation or to begin a PHY level loopback, depending on the power state.
o_txpipe<n>_txelecidle Output Forces transmit output to Electrical Idle when asserted except in loopback. o_txpipe<n>_txdatavalid must be asserted when this signal transitions to either asserted or de-asserted.
o_txpipe<n>_txmargin[2:0] Output
Selects transmitter voltage levels:
  • 000: Normal operating range
  • 001: 800-1200 mV for Full swing* or 400-700mV for Half swing
  • 010: Required and vendor defined
  • 011: Required and vendor defined
  • 100: Required and 200-400 mV for Full swing* or 100-200 mV for Half swing* if the last value or vendor defined
  • 101: Optional and 200-400 mV for Full swing* or 100-200 mV for Half swing* if the last value or vendor defined or Reserved if no other values supported
  • 110: Optional and 200-400 mV for Full swing* or 100-200 mV for Half swing* if the last value or vendor defined or Reserved if no other values supported
  • 111: Optional and 200-400 mV for Full swing* or 100-200 mV for Half swing* if the last value or Reserved if no other values supported
o_txpipe<n>_txoneszeros Output Reserved.
o_txpipe<n>_txstartblock Output

Only used at the 8.0 GT/s signaling rate. Notifies the PHY the starting byte for a 128-bit block.

  • 0: Indicates the byte is not a start of a 128-bit block
  • 1: Indicates the byte is a start of a 128-bit block
o_txpipe<n>_txswing Output
Controls the PHY transmitter voltage swing level:
  • 0: Full swing
  • 1: Low swing

This field is not used at the 8.0 GT/s or higher signaling rates.
o_txpipe<n>_txsyncheader[3:0] Output

Only the lower two bits ([1:0]) are utilized. Provides the sync header for the PHY to use in the next 130b block. The PHY reads this value when the o_txpipe<n>_txstartblock signal is asserted.

This signal is only used at the 8.0 GT/s signaling rates.
o_txpipe<n>_width[2:0] Output
Controls the PIPE datapath width.
  • 0: 8 bits
  • 1: 16 bits
  • 2: 32 bits
  • 3: 64 bits
  • 4: Reserved
Table 131.  RX PIPE Interfacen= [Lane number]
Signal Direction Description
i_rxpipe<n>_dirfeedback[5:0] Input
Provides the link equalization evaluation feedback in the direction change format. Feedback is provided for each coefficient:
  • [1:0]: C-1
  • [3:2]: C0
  • [5:4]: C1
The feedback value for each coefficient is encoded as follows:
  • 00: No change

    01: Increment by 1

  • 10: Decrement by 1
  • 11: Reserved

The feedback C0 is ignored by the PCIe* controller. This signal is only used at the 8.0 GT/s signaling rate.
i_rxpipe<n>_linkevaluationfeedbackfiguremerit[7:0] Input

Provides the PHY link equalization evaluation feedback in the Figure of Merit (FOM) format. The value is encoded as an integer from 0 to 255. An encoding of 0 is the worst, and an encoding of 255 is the best.

This signal is only used at the 8.0 GT/s signaling rate.
i_rxpipe<n>_localfs[5:0] Input Reflects the local FS value advertised by the local PHY.
i_rxpipe<n>_locallf[5:0] Input Reflects the local LF value advertised by the local PHY.
i_rxpipe<n>_localtxcoefficientsvalid Input

This signal must be held high for one PLCK cycle to indicate that the i_rxpipe<n>_localtxpresetcoefficients[17:0] bus correctly represents the coefficients values for the preset on the o_txpipe<n>_localpresetindex[4:0] bus.
i_rxpipe<n>_localtxpresetcoefficients[17:0] Input
These are the coefficients for the preset on the o_txpipe<n>_localpresetindex after a o_txpipe<n>_getlocalpresetcoefficients request.
  • [5:0]: C-1
  • [11:6]: C0
  • [17:12]: C+1
i_rxpipe<n>_p2m_bus[7:0] Input PHY to MAC Communication Bus.
i_rxpipe<n>_pclkchangeok Input The PHY asserts this signal when it is ready for PCLK change in response to MAC changing PCLK rate.
i_rxpipe<n>_phystatus Input Communicates completion of PHY functions, including power management transitions, receiver detection, speed change, and EQ evaluation at Gen3 rate.
i_rxpipe<n>_rxdata[39:0] Input
Parallel received data.
  • Bits 7:0 correspond to the first symbol of the lane.
  • Bits 15:8 correspond to the second symbol of the lane.
  • Bits 39:16 are unused.
i_rxpipe<n>_rxdatak[3:0] Input
Control (K character) indicator bits for received data:
  • Bit 0 corresponds to the first symbol of the lane.
  • Bit 1 corresponds to the second symbol of the lane.
  • Bits 3:2 are unused.

A value of 0 indicates a data byte. A value of 1 indicates a control byte.
i_rxpipe<n>_rxdatavalid Input

Allows the PHY to instruct the MAC to ignore the data interface for one clock cycle. A value of one indicates that the MAC uses the data, a value of zero indicates that the MAC does not use the data.
i_rxpipe<n>_rxelecidlea Input
Indicates receiver detection of an Electrical Idle for the lane.
  • 0: Receive electrical idle is not detected
  • 1: Receive electrical idle is detected

If de-asserted in P2, indicates detection of a beacon.
i_rxpipe<n>_rxstandbystatus Input
Indicates the PHY receiver RxStandbyStatus:
  • 0: Active
  • 1: Standby
i_rxpipe<n>_rxstartblock Input
Only used at the 8.0 GT/s signaling rate. Allows the PHY to indicate the starting byte for a 128-bit block. The starting byte for a 128-bit block always start with Bit 0 of the data interface.
  • 0: Indicates the byte is not a start of a 128-bit block
  • 1: Indicates the byte is a start of a 128-bit block
i_rxpipe<n>_rxstatus[2:0] Input
Encodes receiver status and error codes for the received data stream when receiving data.
  • 000: Received data OK
  • 001: A SKP set has been added
  • 010: A SKP set has been removed
  • 011: Receiver detected
  • 100: Decode error
  • 101: Elastic buffer overflow
  • 110: Elastic buffer underflow
  • 111: Receive disparity error. Not used for Gen3 operation
i_rxpipe<n>_rxsyncheader[3:0] Input

Provides the sync header for the MAC to use with the next 128b block. The MAC reads this value when the i_rxpipe<n>_rxstartblock signal is asserted.

This signal is only used at the 8.0 GT/s signaling rates.
i_rxpipe<n>_rxvalid Input This signal indicates symbol lock and valid data on i_rxpipe<n>_rxdata and i_rxpipe<n>_rxdatak.
Level Two Title