GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

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ID 813754
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. Device Family Support 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks IP 3.4. Configuring and Generating GTS Reset Sequencer IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.10. Power Management x
4.10.1. Endpoint D3 Entry 4.10.2. Endpoint L2 Exit
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
5. IP Parameters x
5.1. System Settings 5.2. PCIe0/PCIe1 5.3. Diagnostics
5.2. PCIe0/PCIe1 x
5.2.1. Interfaces Port 0/Interfaces Port 1 5.2.2. PCIe0/PCIe1 Settings
5.2.1. Interfaces Port 0/Interfaces Port 1 x
5.2.1.1. AXI Interfaces 0/AXI Interface 1 Settings
5.2.2. PCIe0/PCIe1 Settings x
5.2.2.1. PCIe0/PCIe1 Configuration, Debug and Extension Options 5.2.2.2. PCIe0/PCIe1 Base Address Registers 5.2.2.3. PCIe0/PCIe1 Device Identification Registers 5.2.2.4. PCIe0/PCIe1 PCI Express / PCI Capabilities
5.2.2.4. PCIe0/PCIe1 PCI Express / PCI Capabilities x
5.2.2.4.1. PCIe0/PCIe1 Device 5.2.2.4.2. PCIe0/PCIe1 Link 5.2.2.4.3. PCIe0/PCIe1 Slot 5.2.2.4.4. PCIe0/PCIe1 Legacy Interrupt Pin Register 5.2.2.4.5. PCIe0/PCIe1 PTM 5.2.2.4.6. PCIe0/PCIe1 LTR 5.2.2.4.7. PCIe0/PCIe1 MSI 5.2.2.4.8. PCIe0/PCIe1 MSI-X 5.2.2.4.9. PCIe0/PCIe1 PASID 5.2.2.4.10. PCIe0/PCIe1 DEV SER 5.2.2.4.11. PCIe0/PCIe1 PRS 5.2.2.4.12. PCIe0/PCIe1 Power Management 5.2.2.4.13. PCIe0/PCIe1 VSEC 5.2.2.4.14. PCIe0/PCIe1 ATS 5.2.2.4.15. PCIe0/PCIe1 TPH 5.2.2.4.16. PCIe0/PCIe1 ACS 5.2.2.4.17. PCIe0/PCIe1 Hot-Plug 5.2.2.4.18. PCIe0/PCIe1 VIRTIO
5.2.2.4.10. PCIe0/PCIe1 DEV SER x
5.2.2.4.10.1. Implementing Device Serial Number (DSN) with Runtime Update Support
5.2.2.4.18. PCIe0/PCIe1 VIRTIO x
5.2.2.4.18.1. PCIe0/PCIe1 PF<n> VIRTIO STRUCTURES
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Altera-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
B. PIPE Mode Simulation x
B.1. PIPE Mode Interfaces
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

5.2.2.4.1. PCIe0/PCIe1 Device

Table 38.   GTS AXI Streaming IP Parameters: PCIe* 0/ PCIe* 1 Device Tab
Parameter Value Default Setting Description
Maximum payload size supported
  • 128 Bytes
  • 256 Bytes
  • 512 Bytes
 512 Bytes

Sets the read-only value of the max payload size of the Device Capabilities register and optimizes for this payload size.
Function level reset
  • True
  • False
 False Enables function level reset. This option is available when Enable multiple physical functions is enabled. It is enabled by default when Enable SR-IOV support is enabled.
Enable multiple physical functions
  • True
  • False
 False

Enables multiple physical functions.
When you set Enable multiple physical functions to True, the following option is available:

Total physical functions (PFs)

 1–4 1

Sets the number of physical functions (PFs). The IP can support 1–4 PFs.
Enable SR-IOV support
  • True
  • False
 False

Enables the SR-IOV support.

Note: The design compilation may fail with the following error message when you enable the SR-IOV feature without enabling MSI-X or virtual functions.
Attention: Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: hssi_mono_1_0.
When you set Enable SR-IOV support to True, the following option is available:

Total virtual functions of physical function 0 (PF0 VFs)

0–256

Note: 256 is the total virtual functions shared among the physical functions.
0

Sets the number of virtual functions (VFs) to be assigned to the physical functions (PFs).

Example of maximum VFs of the PFs:

If PF0 and PF1 is enabled with PF0 VFs set to 200.

Maximum PF1 VFs = 256 - 200 = 56.
When you set Enable SR-IOV support to True and provide a Total physical functions (PFs) value greater than 1, the following option is available:

Total virtual functions of physical function 1 (PF1 VFs)

 0
When you set Enable SR-IOV support to True and provide a Total physical functions (PFs) value greater than 2, the following option is available:

Total virtual functions of physical function 2 (PF2 VFs)

 0
When you set Enable SR-IOV support to True and provide a Total physical functions (PFs) value greater than 3, the following option is available:

Total virtual functions of physical function 3 (PF3 VFs)

 0
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