GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

ID 813754
Date 8/04/2025
Public
Document Table of Contents

A.2.4.2.3. P0 Configuration Space

This tab allows you to read the configuration space registers for that port. There is a separate tab with the configuration space for each port.

Figure 85. Example of Agilex™ 5 PCIe Configuration Settings