GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs
ID
813754
Date
8/04/2025
Public
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
3.1. Downloading and Installing Quartus® Prime Software
3.2. Configuring and Generating the GTS AXI Streaming IP
3.3. Configuring and Generating GTS System PLL Clocks IP
3.4. Configuring and Generating GTS Reset Sequencer IP
3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs)
3.6. Simulating the GTS AXI Streaming IP Variant
3.7. Compiling the GTS AXI Streaming IP Variant
4.1. Clocking
4.2. Resets
4.3. PCIe* Hard IP
4.4. Hard IP Interface (IF) Adaptor
4.5. Interrupts
4.6. Transaction Ordering
4.7. TX Non-Posted Metering Requirement on Application
4.8. AXI4-Stream Interface
4.9. Tag Allocation
4.10. Power Management
4.11. Config Retry Status Enable
4.12. Hot-Plug
4.13. Configuration Space Extension
4.14. Page Request Service (EP only)
4.15. Precision Time Measurement (PTM)
4.16. Single Root I/O Virtualization (SR-IOV)
4.17. Transaction Layer Packet (TLP) Bypass Mode
4.18. Scalable IOV
5.2.2.4.1. PCIe0/PCIe1 Device
5.2.2.4.2. PCIe0/PCIe1 Link
5.2.2.4.3. PCIe0/PCIe1 Slot
5.2.2.4.4. PCIe0/PCIe1 Legacy Interrupt Pin Register
5.2.2.4.5. PCIe0/PCIe1 PTM
5.2.2.4.6. PCIe0/PCIe1 LTR
5.2.2.4.7. PCIe0/PCIe1 MSI
5.2.2.4.8. PCIe0/PCIe1 MSI-X
5.2.2.4.9. PCIe0/PCIe1 PASID
5.2.2.4.10. PCIe0/PCIe1 DEV SER
5.2.2.4.11. PCIe0/PCIe1 PRS
5.2.2.4.12. PCIe0/PCIe1 Power Management
5.2.2.4.13. PCIe0/PCIe1 VSEC
5.2.2.4.14. PCIe0/PCIe1 ATS
5.2.2.4.15. PCIe0/PCIe1 TPH
5.2.2.4.16. PCIe0/PCIe1 ACS
5.2.2.4.17. PCIe0/PCIe1 Hot-Plug
5.2.2.4.18. PCIe0/PCIe1 VIRTIO
6.1. Overview
6.2. Clocks and Resets
6.3. AXI4-Stream Interfaces
6.4. Configuration Intercept Interface
6.5. Configuration Extension Bus (CEB) Interface
6.6. Control Shadow Interface
6.7. Transmit Flow Control Credit Interface
6.8. Completion Timeout Interface
6.9. Control and Status Register Responder Interface
6.10. Function Level Reset Interface
6.11. TLP Bypass Error Reporting Interface
6.12. Error Interface
6.13. VF Error Flag Interface
6.14. VIRTIO PCI* Configuration Access Interface
6.15. Precision Time Measurement (PTM) Interface
6.16. Serial Data Signals
6.17. Miscellaneous Signals
7.6.1. VF PCI-Compatible Configuration Space Header Type0
7.6.2. VF PCI Express* Capability Structure
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure
7.6.4. VF Alternative Routing ID (ARI) Capability Structure
7.6.5. VF TLP Processing Hints (TPH) Capability Structure
7.6.6. VF Address Translation Services (ATS) Capability Structure
7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.2.1. PCI Express* Capability List Register
7.6.2.2. PCI Express* Device Capabilities Register
7.6.2.3. PCI Express* Device Control and Status Register
7.6.2.4. Link Capabilities Register
7.6.2.5. Link Control and Status Register
7.6.2.6. PCI Express* Device Capabilities 2 Register
7.6.2.7. PCI Express* Device Control and Status 2 Register
7.6.2.8. Link Capabilities 2 Register
7.6.2.9. Link Control and Status 2 Register
A.2.3. Launching the Agilex™ 5 Debug Toolkit
To use the Agilex™ 5 Debug Toolkit, download the .sof file to an Agilex™ 5 device. Then, open the System Console and load the design to the System Console as well. Loading the .sof file to the System Console allows the System Console to communicate with the design using NPDME. NPDME is a JTAG-based Avalon® memory-mapped master. It drives the Avalon® memory-mapped slave interfaces in the PCIe* design. When using NPDME, the Quartus® Prime software inserts the debug interconnect fabric to connect with JTAG.
Here are the steps to complete these tasks:
- Use the Quartus® Prime Programmer to download the .sof file to the Agilex™ 5 device.
Note: To ensure correct operation, use a full installation of the Quartus® Prime Pro Edition software and devices of the same version of the Quartus® Prime Programmer and the Quartus® Prime Pro Edition software that you used to generate the .sof file.Note: A standalone installation of the Quartus® Prime Pro Edition Programmer and Tools does not work.
- To load the design into System Console:
- Launch the Quartus® Prime Pro Edition software.
- Start System Console by choosing Tools, then System Debugging Tools, then System Console.
- On the System Console File menu, select Load design and browse to the .sof file.
- Select the .sof file and click OK. The .sof file loads to the System Console.
- The System Console Toolkit Explorer window lists all the DUTs in the design that have the Agilex™ 5 Debug Toolkit enabled.
- Select the DUT with the Agilex™ 5 Debug Toolkit you want to view. This opens the Debug Toolkit instance of that DUT in the Details window.
- Click agilex5_debug_toolkit to open that instance of the Toolkit. Once the Debug Toolkit is initialized and loaded, the following message in the Messages window appears:
- A new window Main view appears with a view of all the channels in that instance.