GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

ID 813754
Date 8/04/2025
Public
Document Table of Contents

3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs)

Connect the GTS AXI Streaming IP, GTS System PLL Clocks IP, GTS Reset Sequencer IP, and user reset control logic. Add any additional IPs, user logic required in the design and connect the IPs and user logic. You can use Platform Designer and IPs in the IP catalog, or use RTL to design. Also, make appropriate pin assignments to connect ports and set any appropriate per-instance RTL parameters.

Figure 4. Connecting Clock and Reset Signals of GTS AXI Streaming IP
Attention: pin_perst_n shall constitute a reference to the input port for the PERST# function. Refer to Interface Reset Signals section for the port name.
Note: The GTS System PLL Clocks IP and GTS Reset Sequencer IP must be connected to the GTS AXI Streaming IP as shown above.