GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

ID 813754
Date 8/04/2025
Public
Document Table of Contents

A.1. Hardware

Typically, PCI Express* link-up involves the following steps:
  1. Link training
  2. BIOS enumeration and data transfer
The following sections describe the flow to debug link issues during the hardware bring-up. Altera recommends a systematic approach to diagnosing issues as illustrated in the following figure.
Figure 79. PCI Express Debug Flow Chart