GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

ID 813754
Date 8/04/2025
Public
Document Table of Contents

7.6.7.3. Egress Control Vector

Address: Offset 0x8

Table 119.  Egress Control Vector Register Description
Bit Location Description Attributes Default
31:0 Egress Control vector. RO 0x00000000