GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

ID 813754
Date 8/04/2025
Public
Document Table of Contents

3.4. Configuring and Generating GTS Reset Sequencer IP

Following is the process to configure and generate the GTS Reset Sequencer IP. You have to instantiate only one GTS Reset Sequencer IP for all the PCIe* and non- PCIe* channels on a side of the device.

  1. Select GTS Reset Sequencer IP in the IP Catalog.
  2. A New IP Variant window appears. Specify a top-level name for your new custom IP variation. The Parameter Editor saves the IP variation settings in a file named <your_ip>.ip.
  3. Click Create. The Parameter Editor appears. Set the number of banks and lanes.
  4. If the design only has PCIe* channels on a side of the device, select the Enable PCIE and/or HPS USB3.1 only design option.
  5. Set the Number of Lane based on the total number of non- PCIe* channels on the side of the device used in the design. The number of PCIe* channels are not counted in the Number of Lane parameters.
  6. For a PCIe* x8 design, set Number of Bank(s) to 2. For x4/x2/x1 designs, set Number of Bank(s) to 1.
Note: For more descriptions of connecting the GTS Reset Sequencer IP, refer to the Implementing the GTS Reset Sequencer IP section in the GTS Transceiver PHY User Guide .