GTS AXI Streaming IP for PCI Express* User Guide: Agilex™ 5 and Agilex™ 3 FPGAs and SoCs

ID 813754
Date 8/04/2025
Public
Document Table of Contents

7.6.7.1. ACS Extended Capability Header

Address: Offset 0x0

This register contains the PCI Express* Extended Capability ID for ACS Capability, the capability version, and the pointer to the next capability structure.

Table 117.  ACS Extended Capability Description
Bit Location Description Attributes Default
15:0 PCI Express Extended Capability ID. RO 0x000D
19:16 Capability Version. RO 1
31:20

Next Capability Pointer.

Points to Null.

RO Programmable