Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 813663
Date 9/01/2025
Public
Document Table of Contents

1.5.1. Resource Utilization

The estimated resource utilization for all operating modes are obtained by compiling the Low Latency Ethernet 10G MAC IP core with the Quartus® Prime software targeting on Agilex™ 3 and Agilex™ 5 devices. These estimates are generated by the fitter, excluding the virtual I/Os.

Table 4.  Resource Utilization for LL Ethernet 10G MAC for Agilex™ 3 and Agilex™ 5 Devices
MAC Settings ALMs ALUTs Logic Registers Memory Block (M20K)
Operating Mode Enabled Options
10G None. 1940 2900 4000 0
10G Memory-based statistics counters. 2500 3770 5840 4
1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

3300 4500 5750 4
1G/2.5G

IEEE 1588v2 PTP supplementary addresses.

Memory-based statistics counters.

Time of day: 96b and 64b. 5761 7883 12847 14
2.5G

IEEE 1588v2 PTP supplementary addresses.

Memory-based statistics counters.

Time of day: 96b and 64b. 5577 7729 12827 14
1G/10G

Supplementary addresses.

Memory-based statistics counters.

3200 4650 6970 4
1G/2.5G/10G

Supplementary addresses.

Memory-based statistics counters.

3480 4770 7580 4
1G/2.5G/10G

IEEE 1588v2 PTP supplementary addresses.

Memory-based statistics counters.

Time of day: 96b and 64b. 6640 8866 16614 26
10M/100M/1G/2.5G/5G/10G (USXGMII)

Supplementary addresses.

Memory-based statistics counters.

2900 4300 4700 4
10M/100M/1G/2.5G/5G/10G (USXGMII)

IEEE 1588v2 PTP supplementary addresses.

Memory-based statistics counters.

Time of day: 96b and 64b. 5200 6000 8200 21
10M/100M/1G/10G All options enabled except the options to maintain compatibility with the legacy Ethernet 10G MAC. 3580 4910 8360 4
10M/100M/1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

3400 4725 6000 4
10M/100M/1G/2.5G/10G

Supplementary addresses.

Memory-based statistics counters.

3425 5000 8610 10