2.1. Device Footprint
2.2. Power Management
2.3. Configuration
2.4. Design Security Differences
2.5. Logic Elements and Embedded Memory
2.6. PLL and Clock Network
2.7. Digital Signal Processing (DSP)
2.8. I/O Interfaces
2.9. LVDS SERDES Interface
2.10. Sensor Monitoring System
2.11. MIPI D-PHY Interface
2.12. External Memory Interface (EMIF)
2.13. Hard Processor System (HPS)
2.14. Transceiver and Serial Protocols
2.15. PCIe Interface
2.16. Ethernet Interface
2.3.1. General Configuration Pin and Sequences
2.3.2. Device Configuration and the Secure Device Manager (SDM)
2.3.3. Active Serial (AS) Configuration
2.3.4. Avalon® -ST Configuration
2.3.5. JTAG Configuration
2.3.6. Configuration via Protocol (CvP)
2.3.7. QSPI Flash Access and Remote System Upgrade Feature
2.3.8. SEU Features
2.3.9. Configuration File Format Differences
3.3. Upgrading IP Cores and Platform Designer Systems
To migrate your designs from Quartus® Prime Standard Edition to Quartus® Prime Pro Edition, you must upgrade all IP cores and Platform Designer systems.
Quartus® Prime Standard Edition, Quartus® Prime Lite Edition, and the legacy Quartus® II design software products use a proprietary Verilog configuration scheme within the top-level of IP cores and Platform Designer systems for file synthesis. However, the Quartus® Prime Pro Edition does not support this scheme. The following table lists the main differences between the Quartus® Prime software editions:
| Quartus® Prime Standard Edition, Quartus® Prime Lite Edition, and the legacy Quartus® II Design Software | Quartus® Prime Pro Edition |
|---|---|
|
The proprietary Verilog HDL configuration scheme prevents RTL entities from ambiguous instantiation errors during synthesis. However, these errors may manifest in simulation. Resolving this issue requires one of the following:
|
IP and Platform Designer system generation do not use proprietary Verilog HDL configurations and, thus, resolves the issue. The compilation library scheme changes in the following ways:
|