Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 1/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.3.4. Avalon® -ST Configuration

This topic describes key differences between Fast Passive Parallel (FPP) configuration in Cyclone® V devices and Avalon® -ST configuration in Agilex™ 5 devices.

Table 5.  Pin Difference between FPP Configuration and Avalon® -ST Configuration
Configuration Pin Name – Cyclone® V Configuration Pin Name – to Agilex™ 5 Notes for Agilex™ 5 Device
DCLK (PS - FPP) AVST_CLK, SDM_IO14(AVSTx8_CLK)

Avalon® -ST x8 mode has a dedicated clock input on SDM_IO14 (AVSTx8_CLK). For Avalon® -ST x16 mode, use AVST_CLK located in the general-purpose I/O (GPIO) bank.

AVST_CLK and AVSTx8_CLK must be continuous and cannot pause during configuration.

DATA[7:0](FPP8) SDM_IO pins (AVSTx8_DATAn) Avalon® -ST x8 uses Secure Device Manager (SDM) pins for data pins.
DATA[31:0] (FPP32/FPP16) AVST_DATA[15:0] Avalon® -ST x16 uses pins in GPIO bank.
N/A SDM_IO11(AVSTx8_VALID)/AVST_VALID The host must assert AVST_VALID signal when sending a valid AVST_DATA signal and may assert AVST_VALID signal at any time after the assertion of the AVST_READY signal.
N/A SDM_IO8(AVSTx8_READY)/AVST_READY The device asserts the AVST_READY signal when ready to accept data. The host must handle backpressure by monitoring the AVST_READY signal.

The following are other key differences to consider:

  • Use Parallel Flash Loader II (PFL II) Intel® FPGA IP with an external host device in an Agilex™ 5 device.
    Note: Parallel Flash Load (PFL 1) Intel® FPGA IP cannot support Avalon® -ST configuration scheme.
  • The AVST_CLK signal must run continuously during configuration. The AVST_READY signal does not assert unless the clock is running.
  • Host must synchronize the AVST_READY signal (input) to the AVST_CLK signal (output) using a two-stage register synchronizer.
  • Host must drive no more than six data words after the deassertion of the AVST_READY signal, including the two-stage register synchronizer delay incurred.
  • Intel® plans to support the simulation model for the Avalon® -ST controller. The simulation model is essential for simulating Avalon® -ST configuration with their host controller RTL logic during the product development stage.

For additional information, refer to the " Avalon® -ST Configuration" chapter in the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs.

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