Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 1/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.13. Hard Processor System (HPS)

Hard Processor System (HPS) direct migration from Cyclone® V SoC to Agilex™ 5 SoC is not possible due to architectural differences.

Refer to the "HPS Differences Among Intel SoC Device Families" topic in the Agilex™ 5 Hard Processor System Technical Reference Manual to understand the differences for each HPS IP. Intel recommends creating an Agilex™ 5 HPS design from scratch and not from your existing Cyclone® V HPS design.

The following table lists key differences between Cyclone® V and Agilex™ 5 HPS:

Table 22.  HPS Differences
Feature Cyclone® V SoC Agilex™ 5 E-Series/D-Series SoC
Micro Processor Unit (MPU) Single/Dual Cortex* -A9 Dual Cortex* -A76 and dual Cortex* -A55 with DSU
Cache Coherency Controller Accelerator Coherency Port (ACP) CCU
Generic Interrupt Controller (GIC) Supported Supported
System Memory Management Unit (SMMU) Not supported Supported
On-Chip RAM (OCRAM) 64 KB 512 KB
Ethernet Media Access Controller (EMAC) 2 3
DMA Controller 1 2
NAND Flash Controller Supported Supported
SD/eMMC Host Controller Supported Supported
Combo DLL PHY Not supported Supported
Quad SPI Flash Controller Supported inside HPS Not supported (outside of HPS, uses SDM)
USB 3.1 Gen 1 Controller Not supported 1
USB 2.0 OTG Controller 2 1
I3C Controller Not supported 2
I2C Controller 4 5
SPI Controller 2 masters and 2 slaves 2 masters and 2 slaves
Timers 4 4
Watchdog Timers 2 5
UART Controller 2 2
Controller Area Network (CAN) Controller 2 Not supported
General-Purpose I/O Interface (GPIO) Supported Supported
Hard Processor System I/O Pin Multiplexing

Dedicated I/O with Loaner capability for Cyclone® V SoC: 67

Dedicated I/O: 48

Shared I/O: 0
System Manager Supported Supported
Clock Manager Supported Supported
Reset Manager Supported Supported
FPGA Manager Supported Not supported (uses SDM)
Scan Manager Supported Not supported
Security Manager Not supported Not supported (uses SDM)
HPS-to-FPGA Bridges Supported Supported
SDRAM Controller Inside HPS Outside of HPS
System Interconnect Supported Supported
Error Checking and Correction (ECC) Controller Not supported Supported
CoreSight Debug and Trace Supported Supported
Secure Device Manager (SDM) Interface Not supported Supported
Booting and Configuration

Three options:

  • HPS Boot and FPGA Configuration occur separately
  • FPGA Configuration First
  • HPS Boot First

Two options:

  • FPGA Configuration First
  • HPS Boot First

Section Content
HPS Boot Flows

Related Information
Level Two Title