Cyclone® V to Agilex™ 5 Device Migration Guide

Download PDF
ID 787947
Date 1/24/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

4.2. Downloading and Extracting the Design Example

Download and extract the supporting design example files for Cyclone® V to Agilex™ 5 design migration example into a directory on your computer. Do not use spaces in the directory path name.

The CycloneVtoAgilex5MigrationDesignExample.zip file contains the following files:

Table 37.  Design Example Files
File Description
top_cv.qar The archived Cyclone® V design to be migrated to the Agilex™ 5 device.
top_ag5.qar The archived Agilex™ 5 design migrated from the Cyclone® V device. It is included only for your reference.

Block Diagram of the Design

Figure 10. Before Migration: Cyclone® V Design Block Diagram
Figure 11. After Migration: Agilex™ 5 Design Block Diagram

To demonstrate the migration of designs between different device families, the Cyclone® V design (top_cv.qar) contains Intel® FPGA IP cores that can be reused or migrated from the Quartus® Prime Standard Edition to the Pro Edition and IP cores that are not migratable. The design example also includes Nios® IP cores to illustrate the minimal effort required to migrate from the Nios® II processor to Nios® V.

Note: You cannot upgrade IP cores instantiated in the Quartus® Prime Pro Edition software version 23.2.1 to 23.4. Regenerate the instantiated IPs to proceed with your project. However, IP auto-upgrade will upgrade IPs from 23.4 to 24.3 and later releases. For more information, refer to the Quartus® Prime Pro Edition Software and IP Release Notes .
Level Two Title