1.2. HBM2E Interface Intel® FPGA IP v3.0.0

High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Release Notes

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ID 773268

Date 11/04/2024

Version

Public

Table 2. v3.0.0 2023.12.04
Quartus® Prime Version	Description	Impact
23.4	Verified in the Quartus® Prime software v23.4.	Provides interface to high bandwidth memory on Intel Agilex® 7 M-Series FPGAs.

Table 3. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Speed Support Summary
Protocol/Category	Device Speed Grade	Maximum Rate	S	C	T	H
HBM2E	-1	1.6 - 3.2 GT/s	X	X	X ¹	X
	-2	1.6 - 2.8 GT/s	X	X	X ¹	X
	-3	1.6 -2.0 GT/s	X	X	X ¹	X
Note: ¹ = Timing is currently preliminary. It will be necessary to recompile designs in future releases. Support level key: X = supported feature S = simulation support C = compilation support T = timing support H = hardware support

Table 4. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Feature Support Summary
Category	Subcategory	Supported?	S	C	T	H
HBM2E Capacity	8 GB (4H)	Yes	X	X	X	X
HBM2E Capacity	16 GB (8H)	Yes	X	X	X	X
Channels	All eight channels enabled	Yes	X	X	X	X
Channels	Single channel enabled	Yes	X	X	X	X
Protocol	AXI4	Yes	X	X	X	X
Protocol	AXI4-Lite	Yes	X	X	X	X
Dual-HBM2E IP Support	Using design examples	Yes		X	X	X
Data Mode	256 bit	Yes	X	X	X	X
	256 bit with ECC	Yes	X	X	X	X
	256 bit with data mask	Yes	X	X	X	X
	288 bit	Yes	X	X	X	X
Memory Controller	Address Reordering	Yes	X	X	X	X
	Auto-precharge	Yes	X	X	X	X
	Scheduling	Yes	X	X	X	X
	Controller refresh	Yes	X	X	X	X
	Temperature-based throttling	Yes	X	X	X	X
Refresh	Temperature-controlled refresh	Yes	X	X	X	X
Power Estimation		Yes	X	X	X	X
Design Example	1-to-1 full address	Yes	X	X	X	X
	16-to-16 crossbar	Yes	X	X	X	X
	Fabric NoC	Yes	X	X	X	X
	AXI4-Lite	Yes	X	X	X	X
Traffic Generator		Yes	X	X	X	X
Simulators	VCS*	Yes	X
	VCS-MX *	Yes	X
	ModelSim SE *	Yes	X
	Xcelium *	Yes	X
	Aldec *	No
	Questa FE	Yes	X
Support level key: X = supported feature N/A = not applicable S = simulation support C = compilation support T = timing support H = hardware support

Table 5. Intel Agilex® 7 M-Series to Stratix® 10 FPGA HBM Support Comparison
Category	Stratix® 10	Intel Agilex® 7 M-Series	Notes
Memory device	HBM2	HBM2E
Transfer rates	-1: 1.0 - 2.0 GT/s	-1: 1.6 - 3.2 GT/s
	-2: 1.0 - 1.6 GT/s	-2: 1.6 - 2.8 GT/s
	-3: 1.0 - 1.2 GT/s	-3: 1.6 - 2.0 GT/s
Capacity	4 GB/4H and 8 GB/8H	8 GB/4H and 16 GB/8H	Increased capacity per die.
Periphery-to-core transport layer	Hard-wired	Fabric NoC and High-speed interconnect NoC
User interface	Avalon® memory-mapped interface, and AXI	AXI4 and AXI4-Lite
User Clock	150 - 500 MHz	250 - 660 MHz ¹	Valid range depends on device speed grade and complexity of the design.
Configuration interface	8× APB	4× AXI4-Lite	Converged to AXI4 for both main band and side band.
AWORD pins	R[5:0]	R[6:0]
AWORD pins	C[7:0]	C[8:0]
HBMC bypass	ASIC mode, PHY-only mode	None
Refresh	Controller, user-initiated	Controller
¹ = Refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide for information on the user-clock range for different configurations of the HBM2E IP.