1. Publication Deprecation Notice
2. About the SoC Design Example
3. FPGA AI Suite SoC Design Example Quick Start Tutorial
4. FPGA AI Suite SoC Design Example Run Process
5. FPGA AI Suite SoC Design Example Build Process
6. FPGA AI Suite SoC Design Example Quartus® Prime System Architecture
7. FPGA AI Suite Soc Design Example Software Components
8. Streaming-to-Memory (S2M) Streaming Demonstration
A. FPGA AI Suite SoC Design Example User Guide Archives
B. FPGA AI Suite SoC Design Example User Guide Document Revision History
3.1. Initial Setup
3.2. Initializing a Work Directory
3.3. (Optional) Create an SD Card Image (.wic)
3.4. Writing the SD Card Image (.wic) to an SD Card
3.5. Preparing SoC FPGA Development Kits for the FPGA AI Suite SoC Design Example
3.6. Adding Compiled Graphs (AOT files) to the SD Card
3.7. Verifying FPGA Device Drivers
3.8. Running the Demonstration Applications
7.1.1. Yocto Recipe: recipes-core/images/coredla-image.bb
7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbappend
7.1.3. Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb
7.1.4. Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb
7.1.5. Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_%.bbappend
7.1.6. Yocto Recipe: recipes-support/devmem2/devmem2_2.0.bb
7.1.7. Yocto Recipe: wic
6.2.2. RAM considerations
An FPGA-based external memory interface is used to store all machine learning input, output, and intermediate data.
The FPGA AI Suite IP uses the DDR memory extensively in its operations.
Typically, you dedicate a memory to the FPGA AI Suite IP and avoid sharing it with the host CPU DDR memory. Although a design can use the host memory, other services that use the DDR memory impact the FPGA AI Suite IP performance and increase non-determinism in inference durations. Consider this impact when you choose to use a shared DDR resource.
The FPGA AI Suite IP requires an extensive depth of memory that prohibits the use of onboard RAM such as M20Ks. Consider the RAM/DDR memory footprint when you design with the FPGA AI Suite IP.