1. Publication Deprecation Notice
2. About the SoC Design Example
3. FPGA AI Suite SoC Design Example Quick Start Tutorial
4. FPGA AI Suite SoC Design Example Run Process
5. FPGA AI Suite SoC Design Example Build Process
6. FPGA AI Suite SoC Design Example Quartus® Prime System Architecture
7. FPGA AI Suite Soc Design Example Software Components
8. Streaming-to-Memory (S2M) Streaming Demonstration
A. FPGA AI Suite SoC Design Example User Guide Archives
B. FPGA AI Suite SoC Design Example User Guide Document Revision History
3.1. Initial Setup
3.2. Initializing a Work Directory
3.3. (Optional) Create an SD Card Image (.wic)
3.4. Writing the SD Card Image (.wic) to an SD Card
3.5. Preparing SoC FPGA Development Kits for the FPGA AI Suite SoC Design Example
3.6. Adding Compiled Graphs (AOT files) to the SD Card
3.7. Verifying FPGA Device Drivers
3.8. Running the Demonstration Applications
3.3.1. Installing Prerequisite Software for Building an SD Card Image
3.3.2. Building the FPGA Bitstreams
Building the FPGA Bitstreams for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit
Building the FPGA Bitstreams for the Arria® 10 SX SoC FPGA Development Kit
3.3.3. Installing HPS Disk Image Build Prerequisites
3.3.4. (Optional) Downloading the ImageNet Categories
3.3.5. Building the SD Card Image
7.1.1. Yocto Recipe: recipes-core/images/coredla-image.bb
7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbappend
7.1.3. Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb
7.1.4. Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb
7.1.5. Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_%.bbappend
7.1.6. Yocto Recipe: recipes-support/devmem2/devmem2_2.0.bb
7.1.7. Yocto Recipe: wic
3.3.2. Building the FPGA Bitstreams
The FPGA AI Suite SoC design example also includes prebuilt demonstration FPGA bitstreams. If you want to use the prebuilt demonstration bitstreams in your SD card image, skip ahead to Installing HPS Disk Image Build Prerequisites.
If you build your own bitstreams and do not have an FPGA AI Suite IP license, then your bitstream have a limit of 10000 inferences. After 10000 inferences, the unlicensed IP refuses to perform any additional inference. To reset the limit, reprogram the FPGA device.
Building the FPGA Bitstreams for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit
To build the FPGA bitstreams for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit, run the following commands:
dla_build_example_design.py \ -ed 4_AGX7_S2M \ -n 1 \ -a $COREDLA_ROOT/example_architectures/AGX7_Performance.arch \ --build \ --build-dir $COREDLA_WORK/agx7_perf_bitstream \ --output-dir $COREDLA_WORK/agx7_perf_bitstream
The bitstreams built by these commands support both the M2M execution model and the S2M execution model.
Building the FPGA Bitstreams for the Arria® 10 SX SoC FPGA Development Kit
To build the FPGA bitstreams for the Arria® 10 SX SoC FPGA Development Kit, run the following commands:
dla_build_example_design.py \ -ed 4_A10_S2M \ -n 1 \ -a $COREDLA_ROOT/example_architectures/A10_Performance.arch \ --build \ --build-dir $COREDLA_WORK/a10_perf_bitstream \ --output-dir $COREDLA_WORK/a10_perf_bitstream
The bitstreams built by these commands support both the M2M execution model and the S2M execution model.