FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 3/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the FPGA AI Suite PCIe* -based Design Example 4. Building the FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA A. FPGA AI Suite PCIe-based Design Example User Guide Archives B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Arria® 10) 5.5. Programming the FPGA Device ( Agilex™ 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. FPGA AI Suite Runtime 6.3.3. BSP Driver
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

1. FPGA AI Suite PCIe-based Design Example User Guide

Updated for:
Intel® FPGA AI Suite 2024.1

The FPGA AI Suite PCIe* -based Design Example User Guide describes the design and implementation for accelerating AI inference using the FPGA AI Suite, Intel® Distribution of OpenVINO™ toolkit, and an Intel® PAC with Arria® 10 GX FPGA or a Terasic* DE10-Agilex Development Board

The following sections in this document describe the steps to build and execute the design:
The following sections in this document describe design decisions and architectural details about the design:

Use this document to help you understand how to create a PCIe example design with the targeted FPGA AI Suite architecture and number of instances and compiling the design for use with the Intel FPGA Basic Building Blocks (BBBs) system.

About the FPGA AI Suite Documentation Library

Documentation for the FPGA AI Suite is split across a few publications. Use the following table to find the publication that contains the FPGA AI Suite information that you are looking for:
Table 1.   FPGA AI Suite Documentation Library
Title and Description  
Release Notes

Provides late-breaking information about the FPGA AI Suite including new features, important bug fixes, and known issues.

Link
Getting Started Guide

Get up and running with the FPGA AI Suite by learning how to initialize your compiler environment and reviewing the various design examples and tutorials provided with the FPGA AI Suite

Link
IP Reference Manual

Provides an overview of the FPGA AI Suite IP and the parameters you can set to customize it. This document also covers the FPGA AI Suite IP generation utility.

Link
Compiler Reference Manual

Describes the use modes of the graph compiler (dla_compiler). It also provides details about the compiler command options and the format of compilation inputs and outputs.

Link
PCIe-based Design Example User Guide

Describes the design and implementation for accelerating AI inference using the FPGA AI Suite, Intel® Distribution of OpenVINO™ toolkit, and an Intel® PAC with Arria® 10 GX FPGA or a Terasic* DE10-Agilex Development Board.

Link
SoC-based Design Example User Guide

Describes the design and implementation for accelerating AI inference using the FPGA AI Suite, Intel® Distribution of OpenVINO™ toolkit, and an Arria® 10 SX SoC FPGA Development Kit or Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit.

Link

Intel® Distribution of OpenVINO™ toolkit Requirement

To use the FPGA AI Suite, you must be familiar with the Intel® Distribution of OpenVINO™ toolkit.

FPGA AI Suite Version 2024.1 requires the Intel® Distribution of OpenVINO™ toolkit Version 2022.3.1 LTS. For OpenVINO™ documentation, refer to https://docs.openvino.ai/2022.3/documentation.html.

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