2.5.2.1. Parameter Group: Global Parameters
2.5.2.2. Parameter Group: activation
2.5.2.3. Parameter Group: pe_array
2.5.2.4. Parameter Group: pool
2.5.2.5. Parameter Group: depthwise
2.5.2.6. Module: softmax
2.5.2.7. Parameter Group: dma
2.5.2.8. Parameter Group: xbar
2.5.2.9. Parameter Group: filter_scratchpad
2.5.2.10. Parameter Group: input_stream_interface
2.5.2.11. Parameter Group: output_stream_interface
2.5.2.12. Parameter Group: config_network
2.5.2.13. Parameter Group: layout_transform_params
2.6.3. AXI Interface Clock and Reset
Name |
Clock |
Reset |
Note |
---|---|---|---|
DDR0 Initiator |
ddr_clk |
dla_resetn |
N/A |
CSR Responder |
ddr_clk |
dla_resetn |
The CSR initiator operates on the ddr_clk clock. |
Interrupt Initiator |
irq_clk |
dla_resetn |
N/A |
The following parameters are used by the AXI interfaces. The parameter values can be modified in the Architecture Description files as described in IP Generation Utility.
Name |
Supported Value |
Entry in Architecture Description |
---|---|---|
C_CSR_AXI_ADDR_WIDTH |
11 |
= dma.csr_addr_width |
C_CSR_AXI_DATA_WIDTH |
32 |
= dma.csr_data_bytes * 8 |
C_DDR_AXI_ADDR_WIDTH |
1~32 |
= dma.ddr_addr_width |
C_DDR_AXI_BURST_WIDTH |
1~8 |
= dma.ddr_burst_width |
C_DDR_AXI_DATA_WIDTH |
64, 128, 256, 512 (bits) |
= dma.ddr_data_bytes * 8 |
C_DDR_AXI_THREAD_ID_WIDTH |
2 |
= ddr_read_id_width |