2.1. FPGA Simulation Essential Elements
2.2. Overview of Simulation Tool Flow
2.3. Simulation Tool Flow
2.4. Supported Hardware Description Languages
2.5. Supported Simulation Types
2.6. Supported Simulators
2.7. Automating Simulation with the Run Simulation Feature
2.8. Using Precompiled Simulation Libraries
2.7.3.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
2.7.3.2. Optional Simulation Settings for Run Simulation (Batch Mode)
2.7.3.3. Launching Simulation with the Run Simulation Feature
2.7.3.4. Running RTL Simulation using Run Simulation
2.7.3.5. Output Directories and Files for Run Simulation
3.1. Types of Questa*-Intel® FPGA Edition Commands
3.2. Commands to Invoke Questa*-Intel® FPGA Edition
3.3. Commands to Compile, Elaborate, and Simulate
3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation
3.6. Using the Qrun Flow
3.7. Performing RTL Simulation with Questa*-Intel® FPGA Edition
3.8. Performing Gate-Level Simulation with Questa*-Intel® FPGA Edition
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library
3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work)
3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo
3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1
3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg
3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench
3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy
3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
3.8.1. Post-Synthesis and Post-Fit Netlists for Simulation
3.8.2. Files Required for Gate-Level Simulation
3.8.3. Step 1: Generate Gate-Level Netlists for Simulation
3.8.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation
3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation
3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
2.3.5. Commands To Configure and Run Simulation
Once you generate the executable simulation model during elaboration, you can run the executable simulation model to simulate the top-level testbench module.
There are several different methods to configure and run simulation. The following are some of the typical simulator commands and options that you can use for simulation:
- You can specify which signals that you want the simulator to record during simulation. You must ensure that those signals are preserved during the elaboration stage, as Elaboration Options explains.
The simulator writes the waveforms of these signals to a simulator proprietary database during simulation. You can view the waveforms in a GUI after simulation.
Note: You cannot record or display signals in encrypted HDL files with the simulator. - You can specify the amount of simulation time to simulate the top-level testbench module. For example, you can specify a simulation time of 1 milliseconds.
- You can specify an option to wait for simulation licenses. This option is applicable when using floating simulation licenses. Some simulators exit immediately if there are no available floating licenses for simulation.
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