E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 8/08/2023
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP Intel Agilex® 7 Design Example User Guide 2. E-Tile Ethernet IP for Intel Agilex® 7 FPGA Design Example 3. E-tile CPRI PHY Intel® FPGA IP Design Example 4. E-Tile Dynamic Reconfiguration Design Example 5. E-tile Hard IP Intel Agilex® 7 Design Examples User Guide Archives
2. E-Tile Ethernet IP for Intel Agilex® 7 FPGA Design Example x
2.1. Quick Start Guide 2.2. 10GE/25GE with Optional RS-FEC Design Examples 2.3. 100GE with Optional RS-FEC Design Example 2.4. Ethernet Toolkit Overview 2.5. Document Revision History for the E-tile Hard IP for Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design 2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench 2.1.4. Compiling the Compilation-Only Project 2.1.5. Compiling and Configuring the Design Example in Hardware 2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench x
2.1.3.1. Fast Sim Model for E-tile Ethernet IP for Intel Agilex® 7 FPGA
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example x
2.1.6.1. 10GE/25GE Design Example 2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example 2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples x
2.2.1. Simulation Design Examples 2.2.2. Hardware Design Examples 2.2.3. 10GE/25GE Design Example Interface Signals 2.2.4. 10GE/25GE Design Examples Registers
2.2.1. Simulation Design Examples x
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example 2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples x
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components 2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components 2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.3. 100GE with Optional RS-FEC Design Example x
2.3.1. Simulation Design Examples 2.3.2. Hardware Design Examples 2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals 2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals 2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers 2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1. Simulation Design Examples x
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example 2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example 2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example 2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples x
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components 2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example 2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components 2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
2.4. Ethernet Toolkit Overview x
2.4.1. Features
3. E-tile CPRI PHY Intel® FPGA IP Design Example x
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide 3.2. E-tile CPRI PHY Design Example Description 3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example User Guide
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide x
3.1.1. Hardware and Software Requirements 3.1.2. Generating the Design 3.1.3. Directory Structure 3.1.4. Simulating the Design Example Testbench 3.1.5. Compiling the Compilation-Only Project 3.1.6. Compiling and Configuring the Design Example in Hardware 3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description x
3.2.1. Features 3.2.2. Simulation Design Example 3.2.3. Hardware Design Example 3.2.4. Interface Signals 3.2.5. Design Example Register Map for Reconfiguration
4. E-Tile Dynamic Reconfiguration Design Example x
4.1. Quick Start Guide 4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples 4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example 4.4. CPRI Dynamic Reconfiguration Design Examples 4.5. 100G Ethernet Dynamic Reconfiguration Design Example 4.6. Document Revision History for the E-tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design 4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench 4.1.4. Compiling and Configuring the Design Example in Hardware 4.1.5. Testing the E-tile Dynamic Reconfiguration Hardware Design Example
4.1.2. Generating the Design x
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench x
4.1.3.1. Running the Simulation with Default HEX File 4.1.3.2. Running the Simulation with New HEX File 4.1.3.3. Performing the Link Initialization
4.1.5. Testing the E-tile Dynamic Reconfiguration Hardware Design Example x
4.1.5.1. Running the Design Example in Hardware 4.1.5.2. Power Management Setting for Intel Agilex® 7 Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples x
4.2.1. Functional Description 4.2.2. Simulation Design Examples 4.2.3. Hardware Design Examples 4.2.4. 10GE/25GE Design Example Interface Signals 4.2.5. 10GE/25GE Design Examples Registers 4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.2.1. Functional Description x
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples x
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components 4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples x
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components 4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example x
4.3.1. Functional Description 4.3.2. Simulation Design Examples 4.3.3. Hardware Design Examples 4.3.4. 25G Ethernet to CPRI Design Example Interface Signals 4.3.5. 25G Ethernet to CPRI Design Examples Registers 4.3.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.3.1. Functional Description x
4.3.1.1. Clocking Scheme 4.3.1.2. Reset
4.3.2. Simulation Design Examples x
4.3.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.3.3. Hardware Design Examples x
4.3.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.4. CPRI Dynamic Reconfiguration Design Examples x
4.4.1. Functional Description 4.4.2. Simulation Design Examples 4.4.3. Hardware Design Examples 4.4.4. CPRI Design Example Interface Signals 4.4.5. CPRI Design Example Registers 4.4.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.4.1. Functional Description x
4.4.1.1. Clocking Scheme
4.4.2. Simulation Design Examples x
4.4.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components 4.4.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.4.3. Hardware Design Examples x
4.4.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.5. 100G Ethernet Dynamic Reconfiguration Design Example x
4.5.1. Functional Description 4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example 4.5.3. Simulation Design Examples 4.5.4. 100GE DR Hardware Design Examples 4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals 4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers 4.5.7. Steps to Enable FEC 4.5.8. Steps to Disable FEC
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example x
4.5.2.1. Dynamic Reconfiguration Flow in 100G Ethernet Dynamic Reconfiguration Example Design
4.5.3. Simulation Design Examples x
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example 4.5.3.2. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
4.5.4. 100GE DR Hardware Design Examples x
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
4.5.7. Steps to Enable FEC x
4.5.7.1. Configuring for 100G NRZ with RSFEC [KR-FEC (528,514)] 4.5.7.2. Configuring for 100G NRZ with RSFEC [KP-FEC (544,514)] 4.5.7.3. Configuring for 100G PAM4 with RSFEC [KP-FEC (544,514)]
1. About E-tile Hard IP Intel Agilex® 7 Design Example User Guide
2. E-Tile Ethernet IP for Intel Agilex® 7 FPGA Design Example
3. E-tile CPRI PHY Intel® FPGA IP Design Example
4. E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Intel Agilex® 7 Design Examples User Guide Archives

2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example

This hardware design example enables internal serial loopback mode by default. To run the hardware design with external loopback mode, select Enable adaptation load soft IP in the parameter editor before generating the design example.

To turn on the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Intel Agilex® 7 device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
  3. Type source main.tcl to open a connection to the JTAG master.

  4. You can use the following design example commands to configure the 100GE hardware design example test with internal serial loopback mode. For example, in the system console, type run_test and press Enter.

    • run_test 1/run_test_pam4 2: To run hardware design example tests.
    • start_pma_init_adaptation 1/start_pma_02_init_adaptation 2: To perform PMA adaptation.
    • chkphy_status: Displays the clock frequencies and PHY lock status.
    • chkmac_stats: Displays the values in the MAC statistics counters.
    • clear_all_stats: Clears the IP core statistics counters.
    • start_pkt_gen: Starts the packet generator.
    • stop_pkt_gen: Stops the packet generator.
    • loop_on 1/loop_on_pam4 2: Turns on internal serial loopback.
    • loop_off: Turns off internal serial loopback.
    • reg_read <addr>: Returns the IP core register value at <addr>. Example, to read TX datapath PCS ready register, type reg_read 0x322.
    • reg_write <addr> <data>: Writes <data> to the IP core register at address <addr>. Example, to initiate soft reset on RX PCS, type reg_write 0x310 0x0004>
    • chk_init_adaptation_status 1/chk_init_adaptation_status02 2: Check for PAM4 PMA adaptation status.
  5. Optional step: To run the MAC+PCS with (528,514) RS-FEC or (544, 514) RS-FEC and PMA adaptation design example in external loopback mode, open hardware_test_design/hwtest/main.tcl file and uncomment start_pma_init_adaptation_ex 1/start_pma_02_init_adaptation_ex 2 command.

    Make sure the Enable adaptation load soft IP is selected and the PMA adaptation Select is set to:

    • NRZ_28Gbps_LR, NRZ_28Gbps_VSR, or NRZ_10Gbps before generating the design example1
    • PAM4_56Gbps_LR or PAM4_56Gbps_VSR before generating the design example2
  6. Disable the internal serial loopback mode by using loop_off command.

    You can use the following design example commands to configure the 100GE hardware design example test with external loopback mode.

    • start_pma_init_adaptation_ex 1/start_pma_02_init_adaptation_ex 2: Performs PMA adaptation on external loopback or external devices connection tests.
    • start_pma_anlg_rst03 1/start_pma_anlg_02 2: Performs NRZ transceiver PMA reset.
    • init_adaptation_16_NoPrbsNoLdEL03 1/init_adaptation_16_NoPrbsNoLdELCntPC02 2: Performs NRZ PMA adaptation.
      Important: All the values set in this design example are tested with Intel Agilex® 7 F-Series Transceiver-SoC Development Kit . You may need to customize the PMA adaptation configuration values if you are running this design example on boards other than the Intel Agilex® 7 F-Series Transceiver-SoC Development Kit .
    • chk_init_adaptation_status 1/chk_init_adaptation_status_02 2: Checks for PAM4 PMA adaptation status.
    • ld_rcp: Loads PMA configuration settings based on the selection set in the Select a PMA configuration to load or store in the parameter editor.
      Important: All the values set in this design example are tested with Intel Agilex® 7 F-Series Transceiver-SoC Development Kit . You may need to customize the PMA adaptation configuration values if you are running this design example on boards other than the Intel Agilex® 7 F-Series Transceiver-SoC Development Kit .
    • chk_rcp_status 1: Checks PMA configuration settings load status and retry if necessary.
Related Information
1 Applicable for 100GE MAC+PCS with optional (528,514) RS-FEC and PMA adaptation hardware design example.
2 Applicable for 100GE MAC+PCS with optional (544,514) RS-FEC and PMA adaptation hardware design example.
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