1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Stratix® 10 SoC FPGA Boot Flow
8. Stratix® 10 SoC FPGA Boot User Guide Archives
9. Document Revision History for the Stratix® 10 SoC FPGA Boot User Guide
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
2.2.3. Single SDM Flash
The QSPI controller is shared between the SDM and the HPS and only one of these can access the QSPI device at a time. At power-up, the SDM receives access to the QSPI controller. If the HPS needs access to the QSPI flash device, it must request ownership from the SDM through the HPS-to-SDM mailbox.
Software running on the HPS, such as the FSBL, must request permission from the SDM to access the flash attached to the SDM. After the HPS gains ownership of the QSPI controller, it retains ownership until any of the following events occur:
- A power cycle
- A cold reset
- An HPS reboot generated for an RSU event
Figure 4. FPGA Configuration First Layout with Quad SPI