Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 1/15/2025
Public
Document Table of Contents

2.2.3. Single SDM Flash

The QSPI controller is shared between the SDM and the HPS and only one of these can access the QSPI device at a time. At power-up, the SDM receives access to the QSPI controller. If the HPS needs access to the QSPI flash device, it must request ownership from the SDM through the HPS-to-SDM mailbox.

Software running on the HPS, such as the FSBL, must request permission from the SDM to access the flash attached to the SDM. After the HPS gains ownership of the QSPI controller, it retains ownership until any of the following events occur:

  • A power cycle
  • A cold reset
  • An HPS reboot generated for an RSU event
Figure 4. FPGA Configuration First Layout with Quad SPI