Intel® Stratix® 10 SoC FPGA Boot User Guide

Download PDF
ID 683847
Date 1/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
1. Introduction x
1.1. Glossary 1.2. Intel® Stratix® 10 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration - First Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
4.2. Intel® Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
5. Golden System Reference Design and Design Examples x
5.1. Golden System Reference Design 5.2. Bootloader Examples 5.3. Additional Design Examples
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux 6.3. FPGA Partial Reconfiguration from Linux
7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* DS* Intel® SoC FPGA Edition 7.3. Other Debug Considerations
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow
8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives
9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide

4.4. Programming File Generator

The tool that is used for creating the configuration files is called Programming File Generator. This tool is part of the Intel® Quartus® Prime Programmer, which is included with the full Intel® Quartus® Prime software installation. The Intel® Quartus® Prime Programmer can also be downloaded and installed separately as a standalone application, in which case less disk space would be required.

The Programming File Generator tool can be called from command line using the quartus_pfg command, or as a graphical user interface application using qpfgw command. Both command line version and graphical interface version offer the same functionality with a couple of exceptions:
  • Adding an HPS FSBL hex file to a SOF file is only supported by the command line version.
  • Creating the initial flash contents for a Remote System Update (RSU) system is only supported by the graphical interface version.

The command line version is typically more convenient to use, as it requires less parameters to be entered than the graphical interface version. The graphical interface version also has the capability of saving all the selected options in a .pfg file, by going to File > Save or File > Save As menus. The saved .pfg file can later be used to re-create the configuration files by running the quartus_pfg -c filename.pfg command. The .pfg file is an XML file, typically not editable by hand. One useful edit though is to replace absolute filenames with relative ones, so that the tool could be ran in a different folder than the one where the .pfg file was originally created.

The following table summarizes the file types handled by the Intel® Quartus® Prime Programming File Generator:

Table 9.   Intel® Quartus® Prime Programming File Generator File Types
File Extension File Type Description
.jic JTAG Indirect Configuration File These files are intended to be written to QSPI flash by using the Intel® Quartus® Prime Programmer tool. They contain the actual flash data, and also a flash loader, which is a small FPGA design used by the Intel® Quartus® Prime Programmer to write the data.
.rpd Raw Programming Data File These files contain actual binary content for the flash and no additional metadata. They can contain the full content of the flash, similar with the .jic file—this is typically used in the case where an external tool is used to program the initial flash image. They can also contain an RSU application image, or RSU factory update image.
.rbf Raw Binary File

These files are binary files which can be used typically to configure the FPGA fabric for HPS configuration first mode. They can also be used for passively configuring the FPGA device through Avalon® Streaming Interface. They are also used for configuring the FPGA fabric for CvP case.

The maximum size of the .core.rbf file for the FPGA core fabric from the HPS does not exceed the bit-stream size for the FPGA from a configuration device.

The maximum size of bit-stream can be found in the Configuration Bit Stream Sizes section in the Intel® Stratix® 10 Device Data Sheet .

.map Memory Map File These files contain details about where the input data was placed in the output file. This file is human readable.
Related Information
Level Two Title