25G Ethernet Arria® 10 FPGA IP User Guide

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ID 683639
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. 25G Ethernet Intel FPGA IP Supported Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Arria® 10 Devices 2.5.4. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.5. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.4. Link Fault Signaling Interface 4.1.5. 25 GbE RX PCS 4.1.6. Flow Control 4.1.7. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.2. 25 GbE TX PCS x
4.1.2.1. TX RSFEC
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.3.1. IP Core Preamble Processing 4.1.3.2. IP Core Malformed Packet Handling 4.1.3.3. Length/Type Field Processing 4.1.3.4. RX CRC Checking and Dynamic Forwarding
4.1.3.3. Length/Type Field Processing x
4.1.3.3.1. Length Checking
4.1.5. 25 GbE RX PCS x
4.1.5.1. RX RSFEC
4.1.6. Flow Control x
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.6.2. XON/XOFF Pause Frames
4.1.7. 1588 Precision Time Protocol Interfaces x
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.7.2. PTP Receive Functionality 4.1.7.3. PTP Transmit Functionality 4.1.7.4. External Time-of-Day Module for 1588 PTP Variations 4.1.7.5. PTP Timestamp and TOD Formats
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. 1588 PTP Interface Signals 6.7. Miscellaneous Status and Debug Signals 6.8. Reset Signals
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Arria® 10 FPGA IP User Guide Archive
10. Document Revision History for the 25G Ethernet Arria® 10 FPGA IP User Guide

7.6. 1588 PTP Registers

The 1588 PTP registers together with the 1588 PTP signals process and provide Precision Time Protocol (PTP) timestamp information as defined in the IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Standard. The 1588 PTP module provides you the support to implement the 1588 Precision Time Protocol in your design.

Table 28.  TX 1588 PTP Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0xA00 TXPTP_REVID [31:0] IP core revision ID.

0x0916_2016

RO
0xA01 TXPTP_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0xA02 TXPTP_NAME_0 [31:0] First 4 characters of IP core variation identifier string "25GETXPTPCSR"

0x3235_4745

 RO
0xA03 TXPTP_NAME_1 [31:0] Next 4 characters of IP core variation identifier string "25GETXPTPCSR"

0x5458_5054

 RO
0xA04 TXPTP_NAME_2 [31:0] Final 4 characters of IP core variation identifier string "25GETXPTPCSR"

0x5043_5352

 RO
0xA05 TX_PTP_CLK_PERIOD [19:0] clk_txmac clock period.

Bits [19:16]: nanoseconds

Bits [15:0]: fraction of nanosecond

0x28F5C RW

0xA06–0xA0A

 Reserved   Reserved 96'b0 RO
0xA0B TX_PTP_ASYM_DELAY [18:0] Asymmetry adjustment as required for delay measurement. The IP core adds this value to the final delay.
  • Bit[18]: The value of 1 enables the feature and the value of 0 disables the feature.
  • Bit[17]: The value of 1 indicates subtraction and the value of 0 indicates addition. Depending on the value of this bit, the value in bits [16:0] is added to or subtracted from the final delay.
  • Bits[16:0]: Asymmetry adjustment in nanoseconds.
 19'b0 RW
0xA0C TX_PTP_PMA_LATENCY [31:0] Latency through the TX PMA. This is the delay from the TX PCS output to the tx_serial pin.
  • Bits [31:16]: Full nanoseconds
  • Bits [15:0]: Fraction of a nanosecond

In Arria® 10 devices, the TX PMA latency is 187 UI. One UI is approximately 38.8 ps.

Therefore, Altera recommends that you set this register to the value of 0x0007_428F. This is a device-dependent value that is sufficiently accurate in most cases. Altera recommends that you modify this value with extreme caution.

32'b0 RW
Table 29.  RX 1588 PTP Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0xB00 RXPTP_REVID [31:0] IP core revision ID.

0x0916_2016

 RO
0xB01 RXPTP_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0xB02 RXPTP_NAME_0 [31:0] First 4 characters of IP core variation identifier string "25GERXPTPCSR"

0x3235_4745

 RO
0xB03 RXPTP_NAME_1 [31:0] Next 4 characters of IP core variation identifier string "25GERXPTPCSR"

0x5258_5054

 RO
0xB04 RXPTP_NAME_2 [31:0] Final 4 characters of IP core variation identifier string "25GERXPTPCSR"

0x5043_5352

 RO
0xB05 RX_PTP_CLK_PERIOD [19:0] clk_rxmac clock period.

Bits [19:16]: Full nanoseconds

Bits [15:0]: Fraction of a nanosecond

0x28F5C RW
0xB06 RX_PTP_PMA_LATENCY [31:0] Latency through the RX PMA. This is the delay from the rx_serial pin to the RX PCS input.
  • Bits [31:16]: Full nanoseconds
  • Bits [15:0]: Fraction of a nanosecond

In Arria® 10 devices, the RX PMA latency is 102.5 UI. One UI is approximately 38.8 ps.

Therefore, Altera recommends that you set this register to the value of 0x0003_FA1C. This is a device-dependent value that is sufficiently accurate in most cases. Altera recommends that you modify this value with extreme caution.

32'b0 RW
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