3.3.6.1.1. Machine Status Register (mstatus)
3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec)
3.3.6.1.3. Machine Interrupt Register (mip and mie)
3.3.6.1.4. Machine Exception Program Counter Register (mepc)
3.3.6.1.5. Machine Cause Register (mcause)
3.3.6.1.6. Machine Trap Value Register (mtval)
4.3.1. General-Purpose Register File
4.3.2. Shadow Register
4.3.3. Arithmetic Logic Unit
4.3.4. Multipy and Divide Units
4.3.5. Floating-Point Unit
4.3.6. Custom Instruction
4.3.7. Instruction Cycles
4.3.8. Reset and Debug Signals
4.3.9. Control and Status Registers
4.3.10. Trap Controller (CLINT)
4.3.11. Trap Controller (CLIC)
4.3.12. Memory and I/O Organization
4.3.13. RISC-V based Debug Module
4.3.14. Error Correction Code (ECC)
4.3.15. Branch Prediction
4.3.16. Lockstep Module
4.3.10.1.1. Machine Status Register (mstatus)
4.3.10.1.2. Machine Trap-Vector Base-Address Register (mtvec)
4.3.10.1.3. Machine Interrupt Register (mip and mie)
4.3.10.1.4. Machine Exception Program Counter Register (mepc)
4.3.10.1.5. Machine Cause Register (mcause)
4.3.10.1.6. Machine Trap Value Register (mtval)
4.3.10.1.7. Machine Second Trap Value Register (mtval2)
4.3.11.1.3.1. Machine Trap-handler Vector Table base address Register (mtvt)
4.3.11.1.3.2. Machine Next Interrupt Handler Address and Interrupt Enable Register (mnxti)
4.3.11.1.3.3. Machine Interrupt Status Register (mintstatus)
4.3.11.1.3.4. Machine Interrupt-Level Threshold Register (mintthresh)
4.3.11.1.3.5. Machine Scratch Swap for Interrupt-Level Register (mscratchcswl)
4.3.5. Floating-Point Unit
The floating-point unit (FPU) implements the single precision floating point instructions. The FPU operates on data stored in thirty-two 32-bits floating-point registers, implemented using M20K memories.
Below are the characteristics of the FPU:
- Based on RISC-V “F” Standard Extension for Single-Precision Floating-Point
- Supports floating-point fused multiply-add instructions.
- IEEE 754-2008 compliant except for:
- Simplified rounding
- Subnormal supported on a subset of operations
- Consumes resource in a typical system as below1:
- 960 ALMs
- Five M20Ks memories
- Five DSP blocks
Note: The Nios® V/g processor adopts the GNU floating point software emulation for double precision floating point operation.
Register | ABI | Description | Register | ABI | Description |
---|---|---|---|---|---|
f0 | ft0 | FP Temporary 0 | f16 | fa6 | FP Argument 6 |
f1 | ft1 | FP Temporary 1 | f17 | fa7 | FP Argument 7 |
f2 | ft2 | FP Temporary 2 | f18 | fs2 | FP Saved register 2 |
f3 | ft3 | FP Temporary 3 | f19 | fs3 | FP Saved register 3 |
f4 | ft4 | FP Temporary 4 | f20 | fs4 | FP Saved register 4 |
f5 | ft5 | FP Temporary 5 | f21 | fs5 | FP Saved register 5 |
f6 | ft6 | FP Temporary 6 | f22 | fs6 | FP Saved register 6 |
f7 | ft7 | FP Temporary 7 | f23 | fs7 | FP Saved register 7 |
f8 | fs0 | FP Saved register 0 | f24 | fs8 | FP Saved register 8 |
f9 | fs1 | FP Saved register 1 | f25 | fs9 | FP Saved register 9 |
f10 | fa0 |
|
f26 | fs10 | FP Saved register 10 |
f11 | fa1 |
|
f27 | fs11 | FP Saved register 11 |
f12 | fa2 | FP Argument 2 | f28 | ft8 | FP Temporary 8 |
f13 | fa3 | FP Argument 3 | f29 | ft9 | FP Temporary 9 |
f14 | fa4 | FP Argument 4 | f30 | ft10 | FP Temporary 10 |
f15 | fa5 | FP Argument 5 | f31 | ft11 | FP Temporary 11 |
1 System using Arria® 10 FPGA devices.