3.3.6.1.1. Machine Status Register (mstatus)
3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec)
3.3.6.1.3. Machine Interrupt Register (mip and mie)
3.3.6.1.4. Machine Exception Program Counter Register (mepc)
3.3.6.1.5. Machine Cause Register (mcause)
3.3.6.1.6. Machine Trap Value Register (mtval)
4.3.1. General-Purpose Register File
4.3.2. Shadow Register
4.3.3. Arithmetic Logic Unit
4.3.4. Multipy and Divide Units
4.3.5. Floating-Point Unit
4.3.6. Custom Instruction
4.3.7. Instruction Cycles
4.3.8. Reset and Debug Signals
4.3.9. Control and Status Registers
4.3.10. Trap Controller (CLINT)
4.3.11. Trap Controller (CLIC)
4.3.12. Memory and I/O Organization
4.3.13. RISC-V based Debug Module
4.3.14. Error Correction Code (ECC)
4.3.15. Branch Prediction
4.3.16. Lockstep Module
4.3.10.1.1. Machine Status Register (mstatus)
4.3.10.1.2. Machine Trap-Vector Base-Address Register (mtvec)
4.3.10.1.3. Machine Interrupt Register (mip and mie)
4.3.10.1.4. Machine Exception Program Counter Register (mepc)
4.3.10.1.5. Machine Cause Register (mcause)
4.3.10.1.6. Machine Trap Value Register (mtval)
4.3.10.1.7. Machine Second Trap Value Register (mtval2)
4.3.11.1.3.1. Machine Trap-handler Vector Table base address Register (mtvt)
4.3.11.1.3.2. Machine Next Interrupt Handler Address and Interrupt Enable Register (mnxti)
4.3.11.1.3.3. Machine Interrupt Status Register (mintstatus)
4.3.11.1.3.4. Machine Interrupt-Level Threshold Register (mintthresh)
4.3.11.1.3.5. Machine Scratch Swap for Interrupt-Level Register (mscratchcswl)
2.2.5. Error Correction Code (ECC)
The Nios® V/c processor core has the option to enable error detection and ECC status reporting for the RAM block, that is the Register file. Each RAM block has its own source ID. When an ECC event occurs, the processor transmits the source ID and ECC status to the ECC interface.
- If the ECC event is a correctable error, the processor continues to operate after correcting the error. The correction made is not written back to its memory source.
- If the ECC event is an un-correctable error, the processor continues to operate without correcting the error. Thus, it is operating under corrupted data. You need to reset either the processor core alone or the entire system once cpu_ecc_status reports Uncorrectable ECC error.
Note: To reset only the processor core, apply the Reset Request Interface to safely reset the Nios® V processor (cleared of any outstanding operations). To reset the entire system, you can use the hard reset interface instead.
The ECC interface allows external logic to monitor ECC errors from the Nios® V/c processor. The interface is a conduit, made up of the following output signals.
- cpu_ecc_status : Indicates the error status
- cpu_ecc_source : Indicates the error source.
2-bits Encoding | Description | Effects on Software |
---|---|---|
2’b00 | No ECC event | None |
2’b01 | Reserved | Not Applicable |
2’b10 | Correctable single bit ECC error | None |
2’b11 | Un-correctable ECC error | Likely fatal to the processor. |
4-bits Encoding | ECC Source | Available |
---|---|---|
4’b0000 | No ECC event | Always |
4’b0001 | General Purpose Register (GPR) | Always |
4’b0010 ~ 4’b1110 | Other RAM Blocks | Not Available |
4’b1111 | Reserved | Not Applicable |