3.3.6.1.1. Machine Status Register (mstatus)
3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec)
3.3.6.1.3. Machine Interrupt Register (mip and mie)
3.3.6.1.4. Machine Exception Program Counter Register (mepc)
3.3.6.1.5. Machine Cause Register (mcause)
3.3.6.1.6. Machine Trap Value Register (mtval)
4.3.1. General-Purpose Register File
4.3.2. Shadow Register
4.3.3. Arithmetic Logic Unit
4.3.4. Multipy and Divide Units
4.3.5. Floating-Point Unit
4.3.6. Custom Instruction
4.3.7. Instruction Cycles
4.3.8. Reset and Debug Signals
4.3.9. Control and Status Registers
4.3.10. Trap Controller (CLINT)
4.3.11. Trap Controller (CLIC)
4.3.12. Memory and I/O Organization
4.3.13. RISC-V based Debug Module
4.3.14. Error Correction Code (ECC)
4.3.15. Branch Prediction
4.3.16. Lockstep Module
4.3.10.1.1. Machine Status Register (mstatus)
4.3.10.1.2. Machine Trap-Vector Base-Address Register (mtvec)
4.3.10.1.3. Machine Interrupt Register (mip and mie)
4.3.10.1.4. Machine Exception Program Counter Register (mepc)
4.3.10.1.5. Machine Cause Register (mcause)
4.3.10.1.6. Machine Trap Value Register (mtval)
4.3.10.1.7. Machine Second Trap Value Register (mtval2)
4.3.11.1.3.1. Machine Trap-handler Vector Table base address Register (mtvt)
4.3.11.1.3.2. Machine Next Interrupt Handler Address and Interrupt Enable Register (mnxti)
4.3.11.1.3.3. Machine Interrupt Status Register (mintstatus)
4.3.11.1.3.4. Machine Interrupt-Level Threshold Register (mintthresh)
4.3.11.1.3.5. Machine Scratch Swap for Interrupt-Level Register (mscratchcswl)
4.3.14.1. ECC Interface
The ECC interface allows external logic to monitor ECC errors in the Nios® V/g processor. The interface is a conduit and made up of two output signals.
- cpu_ecc_status: Indicates the error status.
- cpu_ecc_source: Indicates the error source
2-bits Encoding | ECC Status | Effects on Software | Next Action |
---|---|---|---|
2’b00 | No ECC event | None | None |
2’b01 | Reserved | Not Applicable | Not Applicable |
2’b10 | Correctable single bit ECC error | None | None |
2’b11 | Un-correctable ECC error | Likely fatal and halts processor | Reset either processor or entire system |
4-bits Encoding | ECC Source | Available |
---|---|---|
4’b0000 | No ECC event | Always |
4’b0001 | General Purpose Register (GPR) | Always |
4’b0010 | Instruction Cache Data RAM | Always |
4’b0011 | Instruction Cache Tag RAM | Always |
4’b0100 | Data Cache Data RAM | Always |
4’b0101 | Data Cache Tag RAM | Always |
4’b0110 | Instruction TCM1 | When Instruction TCM1 is present |
4’b0111 | Instruction TCM2 | When Instruction TCM2 is present |
4’b1000 | Data TCM1 | When Data TCM1 is present |
4’b1001 | Data TCM2 | When Data TCM2 is present |
4’b1010 | Floating Point Register (FPR) | When FPU is present |
4’b1111 | Reserved | Not Applicable |