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2.1. Installation and Licensing
2.2. Generating a CPRI IP
2.3. CPRI IP Parameters
2.4. Integrating the CPRI IP into your Design: Required External Blocks
2.5. Simulating Intel FPGA IP Cores
2.6. Running the CPRI IP Design Example
2.7. CPRI IP Design Example Clocks
2.8. About the Testbench
2.9. Compiling the Full Design and Programming the FPGA
2.4.1. Adding the Transceiver TX PLL IP
2.4.2. Adding the Reset Controller
2.4.3. Adding the Transceiver Reconfiguration Controller
2.4.4. Adding the Off-Chip Clean-Up PLL
2.4.5. Adding and Connecting the Single-Trip Delay Calibration Blocks
2.4.6. CPRI IP Transceiver PLL Calibration
2.4.7. Reference and System PLL Clock for your IP Design
3.1. Interfaces Overview
3.2. CPRI IP Clocking Structure
3.3. CPRI IP Reset Requirements
3.4. Start-Up Sequence Following Reset
3.5. AUX Interface
3.6. Direct IQ Interface
3.7. Ctrl_AxC Interface
3.8. Direct Vendor Specific Access Interface
3.9. Real-Time Vendor Specific Interface
3.10. Direct HDLC Serial Interface
3.11. Direct L1 Control and Status Interface
3.12. L1 Debug Interface
3.13. Media Independent Interface (MII) to External Ethernet Block
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block
3.15. CPU Interface to CPRI IP Registers
3.16. Auto-Rate Negotiation
3.17. Extended Delay Measurement
3.18. CPRI IP Deterministic Latency
3.19. CPRI IP Transceiver and Transceiver Management Interfaces
3.20. Testing Features
3.19.1. CPRI Link
3.19.2. Main Transceiver Clock and Reset Signals
3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface
3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface
3.19.5. RS-FEC Interface
3.19.6. Interface to the External Reset Controller
3.19.7. Interface to the External PLL
3.19.8. Transceiver Debug Interface
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3.12. L1 Debug Interface
If you turn on Enable L1 debug interfaces in the CPRI parameter editor, the L1 debug interface is available.
Signal Name |
Direction |
Description |
---|---|---|
rx_lcv | Output | Indicates the IP core has detected excessive 8B10B errors received. The IP core asserts this signal when it detects more than 15 bits of error. |
rx_freq_alarm | Output | Indicates the CPRI receive clock (receiver CDR recovered clock) and the main IP core clock (cpri_clkout) have a PPM difference. The IP core asserts this alarm each time it detects a mismatch. |