1.1. Configuration Methods
1.2. Specifications
1.3. FIFO Functional Timing Requirements
1.4. SCFIFO ALMOST_EMPTY Functional Timing
1.5. FIFO Output Status Flag and Latency
1.6. FIFO Metastability Protection and Related Options
1.7. FIFO Synchronous Clear and Asynchronous Clear Effect
1.8. SCFIFO and DCFIFO Show-Ahead Mode
1.9. Different Input and Output Width
1.10. DCFIFO Timing Constraint Setting
1.11. Coding Example for Manual Instantiation
1.12. Design Example
1.13. Gray-Code Counter Transfer at the Clock Domain Crossing
1.14. Guidelines for Embedded Memory ECC Feature
1.15. FIFO Intel® FPGA IP User Guide Archives
1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide
1.14. Guidelines for Embedded Memory ECC Feature
The FIFO Intel® FPGA IP cores support embedded memory ECC for M20K memory blocks. The built-in ECC feature in the devices can perform:
- Single-error detection and correction
- Double-adjacent-error detection and correction
- Triple-adjacent-error detection
You can turn on FIFO Embedded ECC feature by enabling enable_ecc parameter in the FIFO Intel® FPGA IP GUI.
Note: Embedded memory ECC feature is only available for M20K memory block type.
Note: The embedded memory ECC supports variable data width. When ECC is enabled, RAM combines multiple M20K blocks in the configuration of 32 (width) x 512 (depth) to fulfill your instantiation. The unused data width is tied to the VCC internally.
Note: The embedded memory ECC feature is not supported in mixed-width mode.
Figure 15. ECC Option in FIFO Intel® FPGA IP GUI
When you enable the ECC feature, a 2-bit wide error correction status port (eccstatus[1:0]) is created in the generated FIFO entity. These status bits indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit.
- 00: No error
- 01: Illegal
- 10: A correctable error occurred and the error has been corrected at the outputs; however, the memory array has not been updated.
- 11: An uncorrectable error occurred and uncorrectable data appears at the output