FIFO Intel® FPGA IP User Guide

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ID 683522
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. FIFO Intel® FPGA IP User Guide
1. FIFO Intel® FPGA IP User Guide x
1.1. Configuration Methods 1.2. Specifications 1.3. FIFO Functional Timing Requirements 1.4. SCFIFO ALMOST_EMPTY Functional Timing 1.5. FIFO Output Status Flag and Latency 1.6. FIFO Metastability Protection and Related Options 1.7. FIFO Synchronous Clear and Asynchronous Clear Effect 1.8. SCFIFO and DCFIFO Show-Ahead Mode 1.9. Different Input and Output Width 1.10. DCFIFO Timing Constraint Setting 1.11. Coding Example for Manual Instantiation 1.12. Design Example 1.13. Gray-Code Counter Transfer at the Clock Domain Crossing 1.14. Guidelines for Embedded Memory ECC Feature 1.15. FIFO Intel® FPGA IP User Guide Archives 1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide
1.2. Specifications x
1.2.1. Verilog HDL Prototype 1.2.2. VHDL Component Declaration 1.2.3. VHDL LIBRARY-USE Declaration 1.2.4. FIFO Signals 1.2.5. FIFO Parameter Settings
1.7. FIFO Synchronous Clear and Asynchronous Clear Effect x
1.7.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
1.10. DCFIFO Timing Constraint Setting x
1.10.1. Embedded Timing Constraint 1.10.2. User Configurable Timing Constraint
1.10.2. User Configurable Timing Constraint x
1.10.2.1. SDC Commands
1. FIFO Intel® FPGA IP User Guide

1.10.1. Embedded Timing Constraint

When using the Quartus® Prime Timing Analyzer with a design that contains a DCFIFO block apply the following false paths to avoid timing failures in the synchronization registers:
  • For paths crossing from the write into the read domain, apply a false path assignment between the delayed_wrptr_g and rs_dgwp registers:

    set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}]

  • For paths crossing from the read into the write domain, apply a false path assignment between the rdptr_g and ws_dgrp registers:

    set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]

The false path assignments are automatically added through the HDL-embedded Synopsis design constraint (SDC) commands when you compile your design. The related message is shown under the Timing Analyzer report.

Note: The constraints are internally applied but are not written to the Synopsis Design Constraint File (.sdc). To view the embedded-false path, type report_sdc in the console pane of the Timing Analyzer GUI.

If you use the Quartus® Prime Timing Analyzer, the false paths are applied automatically for the DCFIFO.

Note: If the DCFIFO is implemented in ALMs, you can ignore the cross-domain timing violations from the data path of the DFFE array (that makes up the memory block) to the q output register. To ensure the q output is valid, sample the output only after the rdempty signal is deasserted.
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